diff options
| author | Felix Singer <felixsinger@posteo.net> | 2023-10-26 15:42:16 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-10-30 14:00:48 +0000 |
| commit | ee1fd54aef8ec0aba9e3dc01111251e1ae6b9d12 (patch) | |
| tree | c80d54121beec1c097e124ed7f3891edb71333ad /src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb | |
| parent | d163253ba047515e3317e9da38aa7cc5714a7f0c (diff) | |
mb/system76/{tgl,skl}/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.
While on it, remove superfluous comments related to modified lines.
Change-Id: I75aeb46ea3b4a7c0a41dce375735e7b42ed59587
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78664
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb')
| -rw-r--r-- | src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb | 34 |
1 files changed, 19 insertions, 15 deletions
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb index 58cf708067..d03bd2e432 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb @@ -29,23 +29,27 @@ chip soc/intel/tigerlake register "PcieClkSrcClkReq[4]" = "4" end device ref south_xhci on - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right) - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right) - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left) - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left) - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left) + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Right) */ + [1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */ + [3] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Left) */ + [4] = USB2_PORT_MID(OC_SKIP), /* USB 2.0 (Left) */ + [5] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */ + [7] = USB2_PORT_MID(OC_SKIP), /* Camera */ + [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 (Right) */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Left) */ + }" end device ref sata on - register "SataPortsEnable[0]" = "1" # HDD (SATA0B) - register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A) + register "SataPortsEnable" = "{ + [0] = 1, /* HDD (SATA0B) */ + [1] = 1, /* SSD1 (SATA1A) */ + }" end device ref pcie_rp5 on # PCIe root port #5 x1, Clock 5 (GLAN) |