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authorFelix Singer <felixsinger@posteo.net>2023-10-26 15:42:16 +0200
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2023-10-30 14:00:48 +0000
commitee1fd54aef8ec0aba9e3dc01111251e1ae6b9d12 (patch)
treec80d54121beec1c097e124ed7f3891edb71333ad /src/mainboard/system76/tgl-h/variants
parentd163253ba047515e3317e9da38aa7cc5714a7f0c (diff)
mb/system76/{tgl,skl}/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they should stay in the device scope of them. While on it, remove superfluous comments related to modified lines. Change-Id: I75aeb46ea3b4a7c0a41dce375735e7b42ed59587 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78664 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/system76/tgl-h/variants')
-rw-r--r--src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb34
-rw-r--r--src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb34
-rw-r--r--src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb28
3 files changed, 53 insertions, 43 deletions
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
index 58cf708067..d03bd2e432 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
@@ -29,23 +29,27 @@ chip soc/intel/tigerlake
register "PcieClkSrcClkReq[4]" = "4"
end
device ref south_xhci on
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right)
- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right)
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left)
- register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right)
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right)
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right)
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Right) */
+ [1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */
+ [3] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
+ [4] = USB2_PORT_MID(OC_SKIP), /* USB 2.0 (Left) */
+ [5] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 (Right) */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
+ }"
end
device ref sata on
- register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
- register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
+ register "SataPortsEnable" = "{
+ [0] = 1, /* HDD (SATA0B) */
+ [1] = 1, /* SSD1 (SATA1A) */
+ }"
end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 5 (GLAN)
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
index 7bcb51cc6b..b463fe7b7b 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
@@ -29,23 +29,27 @@ chip soc/intel/tigerlake
register "PcieClkSrcClkReq[7]" = "7"
end
device ref south_xhci on
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 2 (Right)
- register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Back)
- register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left)
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right)
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Back)
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 2 (Right) */
+ [1] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
+ [2] = USB2_PORT_TYPE_C(OC_SKIP), /* USB 3.2 Gen 2 Type C (Back) */
+ [5] = USB2_PORT_MID(OC_SKIP), /* USB 2.0 (Left) */
+ [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [8] = USB2_PORT_MID(OC_SKIP), /* Per-Key */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 (Right) */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 Type C (Back) */
+ }"
end
device ref sata on
- register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
- register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A)
+ register "SataPortsEnable" = "{
+ [0] = 1, /* HDD (SATA0B) */
+ [1] = 1, /* SSD2 (SATA1A) */
+ }"
end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 8 (GLAN)
diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
index 87311d97a8..6f25d7bb7c 100644
--- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
@@ -41,19 +41,21 @@ chip soc/intel/tigerlake
end
device ref tbt_dma0 on end # TYPEC1
device ref south_xhci on
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 1)
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 2)
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 1)
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 2)
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
+ [2] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Right 1) */
+ [3] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Right 2) */
+ [4] = USB2_PORT_MID(OC_SKIP), /* Per-Key */
+ [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [8] = USB2_PORT_TYPE_C(OC_SKIP), /* TYPEC1 */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Right 1) */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Right 2) */
+ }"
end
device ref sata on
register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 22:01:39 +0000