mb/system76/rpl: Add Lemur Pro 12 as a variant

The Lemur Pro 12 (lemp12) is a Raptor Lake-U board.

Tested with a custom edk2 UefiPayloadPkg.

Working:

- PS/2 keyboard
- I2C HID touchpad
- DIMM slot with 4800 MT/s memory
- Both SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone + mic audio
- 3.5mm microphone input
- S3 suspend/resume
- TPM 2.0 device
- Booting Pop!_OS Linux 22.04 with kernel 6.2.7

Not working:

- Onboard RAM

Change-Id: I0c4941534b719ea8fc93eb3492d5fe16db208647
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 388 insertions, 0 deletions

diff --git a/src/mainboard/system76/rpl/variants/lemp12/board.fmd b/src/mainboard/system76/rpl/variants/lemp12/board.fmd
new file mode 100644
index 0000000000..fdf1ebdf52
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/lemp12/board.fmd
@@ -0,0 +1,12 @@
+FLASH 32M {
+	SI_DESC 4K
+	SI_ME 4824K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 256K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}
diff --git a/src/mainboard/system76/rpl/variants/lemp12/board_info.txt b/src/mainboard/system76/rpl/variants/lemp12/board_info.txt
new file mode 100644
index 0000000000..0698cc3459
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/lemp12/board_info.txt
@@ -0,0 +1,2 @@
+Board name: lemp12
+Release year: 2023
diff --git a/src/mainboard/system76/rpl/variants/lemp12/data.vbt b/src/mainboard/system76/rpl/variants/lemp12/data.vbt
new file mode 100644
index 0000000000..ea0331c7db
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/lemp12/data.vbt
diff --git a/src/mainboard/system76/rpl/variants/lemp12/gpio.c b/src/mainboard/system76/rpl/variants/lemp12/gpio.c
new file mode 100644
index 0000000000..e8eb1e20a8
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/lemp12/gpio.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_NC(GPD2, NONE),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD7_REST
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	PAD_NC(GPP_A6, NONE),
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_NC(GPP_A11, NONE),
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
+	PAD_NC(GPP_A14, NONE),
+	PAD_NC(GPP_A15, NONE),
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
+	PAD_NC(GPP_A17, NONE),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_CFG_GPI(GPP_A22, NONE, DEEP), // SSD2_PCIE_WAKE#
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), // VRALERT#
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	// GPP_B9 missing
+	// GPP_B10 missing
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // Top swap override
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_CFG_GPO(GPP_B17, 1, PLTRST), // WLAN_RST#
+	PAD_NC(GPP_B18, NONE), // NO REBOOT strap
+	// GPP_B19 missing
+	// GPP_B20 missing
+	// GPP_B21 missing
+	// GPP_B22 missing
+	PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // CMB_DATA_DDR
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST), // TLS CONFIDENTIALITY strap
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+	PAD_NC(GPP_C5, NONE), // ESPI OR EC LESS strap
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA
+	// GPP_C8 missing
+	// GPP_C9 missing
+	// GPP_C10 missing
+	// GPP_C11 missing
+	// GPP_C12 missing
+	// GPP_C13 missing
+	// GPP_C14 missing
+	// GPP_C15 missing
+	// GPP_C16 missing
+	// GPP_C17 missing
+	// GPP_C18 missing
+	// GPP_C19 missing
+	// GPP_C20 missing
+	// GPP_C21 missing
+	// GPP_C22 missing
+	// GPP_C23 missing
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	// GPP_D5 (SSD0_CLKREQ#) configured by FSP
+	// GPP_D6 (SSD1_CLKREQ#) configured by FSP
+	// GPP_D7 (WLAN_CLKREQ#) configured by FSP
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD2_PWR_EN
+	PAD_NC(GPP_D15, NONE),
+	PAD_CFG_GPO(GPP_D16, 1, DEEP), // SSD1_PWR_EN
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_GPO(GPP_D19, 0, DEEP), // SATA_LED#
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_NC(GPP_E2, NONE),
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST), // WIFI_RF_EN
+	PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_GPO(GPP_E6, 0, DEEP), // JTAG ODT DISABLE strap
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+	PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+	PAD_NC(GPP_E10, NONE),
+	PAD_CFG_GPI(GPP_E11, NONE,  DEEP), // BOARD_ID1
+	PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_NC(GPP_E13, NONE),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_NC(GPP_E17, NONE),
+	// GPP_E18 (TBT_LSX0_TXD) configured by FSP
+	// GPP_E19 (TBT_LSX0_RXD) configured by FSP
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE),
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+	// GPP_F5 (CNVI_CLKREQ) configured by FSP
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
+	// GPP_F8 missing
+	PAD_NC(GPP_F9, NONE),
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST), // CARD_RTD3_RST#
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_CFG_GPO(GPP_F17, 1, PLTRST), // GPIO_SDCARD_EN
+	PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP#
+	// GPP_F19 (CARD_CLKREQ#) configured by FSP
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD2_RST#
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST), // MS_SSD1_RST#
+	PAD_NC(GPP_H1, NONE),
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST), // WLAN_RST#
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
+	// GPP_H10 (UART0_RX) configured in bootblock
+	// GPP_H11 (UART0_TX) configured in bootblock
+	PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), // SATA1_DEVSLP1
+	PAD_NC(GPP_H13, NONE),
+	// GPP_H14 missing
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	// GPP_H16 missing
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H19, NONE),
+	PAD_CFG_GPO(GPP_H20, 0, DEEP), // PM_CLKRUN#
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_NC(GPP_H23, NONE),
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE), // DMIC_CLK
+	PAD_NC(GPP_R7, NONE), // DMIC_DAT
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/rpl/variants/lemp12/gpio_early.c b/src/mainboard/system76/rpl/variants/lemp12/gpio_early.c
new file mode 100644
index 0000000000..c80c798b04
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/lemp12/gpio_early.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/rpl/variants/lemp12/hda_verb.c b/src/mainboard/system76/rpl/variants/lemp12/hda_verb.c
new file mode 100644
index 0000000000..12fddf42f8
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/lemp12/hda_verb.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256, /* Vendor ID */
+	0x15587724, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15587724),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb
new file mode 100644
index 0000000000..6f6ede508a
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb
@@ -0,0 +1,83 @@
+chip soc/intel/alderlake
+	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 46,
+	}"
+
+	device domain 0 on
+		subsystemid 0x1558 0x7724 inherit
+
+		device ref tbt_pcie_rp0 on end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+		end
+		device ref tcss_dma0 on end
+		device ref xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Left
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Right
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Left
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Right
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
+		end
+
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+
+		device ref pcie4_0 on
+			# CPU RP#1 x4, Clock 0 (SSD2)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp5 on
+			# PCH RP#5 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp6 on
+			# PCH RP#6 x1, Clock 6 (CARD)
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp9 on
+			# PCH RP#9 x4, Clock 1 (SSD1)
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+	end
+end
diff --git a/src/mainboard/system76/rpl/variants/lemp12/romstage.c b/src/mainboard/system76/rpl/variants/lemp12/romstage.c
new file mode 100644
index 0000000000..c8c623fc19
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/lemp12/romstage.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR5,
+		.ect = true,
+		.LpDdrDqDqsReTraining = 1,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_MIXED,
+		.cbfs_index = 0,
+		.smbus[1] = { .addr_dimm[0] = 0x52, },
+	};
+	const bool half_populated = false;
+
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}