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Diffstat (limited to 'src/mainboard/system76/rpl/variants/lemp12/overridetree.cb')
-rw-r--r--src/mainboard/system76/rpl/variants/lemp12/overridetree.cb83
1 files changed, 83 insertions, 0 deletions
diff --git a/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb
new file mode 100644
index 0000000000..6f6ede508a
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb
@@ -0,0 +1,83 @@
+chip soc/intel/alderlake
+ register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
+ .tdp_pl1_override = 15,
+ .tdp_pl2_override = 46,
+ }"
+
+ device domain 0 on
+ subsystemid 0x1558 0x7724 inherit
+
+ device ref tbt_pcie_rp0 on end
+ device ref tcss_xhci on
+ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+ end
+ device ref tcss_dma0 on end
+ device ref xhci on
+ # USB2
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Left
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Right
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+ # USB3
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Left
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Right
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
+ end
+
+ device ref i2c0 on
+ # Touchpad I2C bus
+ register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+ chip drivers/i2c/hid
+ register "generic.hid" = ""ELAN0412""
+ register "generic.desc" = ""ELAN Touchpad""
+ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)"
+ register "generic.detect" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 15 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""FTCS1000""
+ register "generic.desc" = ""FocalTech Touchpad""
+ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)"
+ register "generic.detect" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 38 on end
+ end
+ end
+
+ device ref pcie4_0 on
+ # CPU RP#1 x4, Clock 0 (SSD2)
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .clk_src = 0,
+ .clk_req = 0,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end
+ device ref pcie_rp5 on
+ # PCH RP#5 x1, Clock 2 (WLAN)
+ register "pch_pcie_rp[PCH_RP(5)]" = "{
+ .clk_src = 2,
+ .clk_req = 2,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end
+ device ref pcie_rp6 on
+ # PCH RP#6 x1, Clock 6 (CARD)
+ register "pch_pcie_rp[PCH_RP(6)]" = "{
+ .clk_src = 6,
+ .clk_req = 6,
+ .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end
+ device ref pcie_rp9 on
+ # PCH RP#9 x4, Clock 1 (SSD1)
+ register "pch_pcie_rp[PCH_RP(9)]" = "{
+ .clk_src = 1,
+ .clk_req = 1,
+ .flags = PCIE_RP_LTR,
+ }"
+ end
+ end
+end