diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 03:39:24 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:44:02 +0000 |
| commit | dcddc53fde2d559beef998d3c17e9b7a227e3665 (patch) | |
| tree | f3061a3764892f73bc5dd827134a795c275b685f /src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb | |
| parent | 6c83a71b0a803c922b02b613e927d4c49b944c32 (diff) | |
skl mainboards/dt: Move genx_dec settings into LPC device scope
Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb')
| -rw-r--r-- | src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 035811f9bf..97f995d7cd 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -8,9 +8,6 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x007c0a01" # Super IO SWC - register "gen2_dec" = "0x000c0ca1" # IPMI KCS - # FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1" @@ -67,6 +64,9 @@ chip soc/intel/skylake smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end device ref lpc_espi on + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + chip drivers/ipmi use pch_gpio as gpio_dev register "post_complete_gpio" = "GPP_B20" |