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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-06-15 14:43:27 +0200 |
|---|---|---|
| committer | Jakub Czapiga <jacz@semihalf.com> | 2023-06-19 11:10:19 +0000 |
| commit | c7beb4f3176dc0e3cf26be46a7385b6352ba3b2b (patch) | |
| tree | a1f3b5ca2c9f7c0572e6ad8055ca716e2ffb92f8 /src/mainboard/siemens/mc_apl1/variants | |
| parent | 53ad07a1eccefd80d0fc21c2103ced1f23573de2 (diff) | |
soc/intel/apollolake: Switch to snake case for DisableSataSalpSupport
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'DisableSataSalpSupport'.
Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75858
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1/variants')
7 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index 5d4acd85ab..e5544a10eb 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -71,7 +71,7 @@ chip soc/intel/apollolake device pci 12.0 on # - SATA register "sata_ports_enable[0]" = "1" register "sata_ports_enable[1]" = "1" - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 - MACPHY register "pcie_rp_clkreq_pin[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 7054413305..ae9c3b162c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -71,7 +71,7 @@ chip soc/intel/apollolake register "sata_ports_enable[1]" = "1" register "sata_ports_ssd[0]" = "1" register "sata_ports_ssd[1]" = "1" - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index 472f5baddc..74e30bb3aa 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -66,7 +66,7 @@ chip soc/intel/apollolake device pci 12.0 on # - SATA register "sata_ports_enable[0]" = "1" register "sata_ports_enable[1]" = "1" - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index baaff1e960..e5d80beef4 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -60,7 +60,7 @@ chip soc/intel/apollolake device pci 12.0 on # - SATA register "sata_ports_enable[0]" = "1" register "sata_ports_enable[1]" = "1" - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 52fcd49df6..87e4cc2f41 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -71,7 +71,7 @@ chip soc/intel/apollolake register "sata_ports_enable[1]" = "1" register "sata_ports_ssd[0]" = "1" register "sata_ports_ssd[1]" = "1" - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index dc66be63bd..86e92d5289 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -42,7 +42,7 @@ chip soc/intel/apollolake register "sata_ports_enable[1]" = "1" register "sata_ports_ssd[0]" = "1" register "sata_ports_ssd[1]" = "1" - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb index 0a080c3a63..6cf285f1d8 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb @@ -58,7 +58,7 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" |