soc/intel/apollolake: Switch to snake case for DisableSataSalpSupport

For a unification of the naming convension, change from pascal case to
snake case style for parameter 'DisableSataSalpSupport'.

Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75858
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

9 files changed, 9 insertions, 9 deletions

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
index 5d4acd85ab..e5544a10eb 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
@@ -71,7 +71,7 @@ chip soc/intel/apollolake
 		device pci 12.0 on	# - SATA
 			register "sata_ports_enable[0]" = "1"
 			register "sata_ports_enable[1]" = "1"
-			register "DisableSataSalpSupport" = "1"
+			register "disable_sata_salp_support" = "1"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0 - MACPHY
 			register "pcie_rp_clkreq_pin[2]" = "0"
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
index 7054413305..ae9c3b162c 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
@@ -71,7 +71,7 @@ chip soc/intel/apollolake
 			register "sata_ports_enable[1]" = "1"
 			register "sata_ports_ssd[0]" = "1"
 			register "sata_ports_ssd[1]" = "1"
-			register "DisableSataSalpSupport" = "1"
+			register "disable_sata_salp_support" = "1"
 			register "sata_speed" = "SATA_GEN2"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
index 472f5baddc..74e30bb3aa 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
@@ -66,7 +66,7 @@ chip soc/intel/apollolake
 		device pci 12.0 on	# - SATA
 			register "sata_ports_enable[0]" = "1"
 			register "sata_ports_enable[1]" = "1"
-			register "DisableSataSalpSupport" = "1"
+			register "disable_sata_salp_support" = "1"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0
 			register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
index baaff1e960..e5d80beef4 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
@@ -60,7 +60,7 @@ chip soc/intel/apollolake
 		device pci 12.0 on	# - SATA
 			register "sata_ports_enable[0]" = "1"
 			register "sata_ports_enable[1]" = "1"
-			register "DisableSataSalpSupport" = "1"
+			register "disable_sata_salp_support" = "1"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0
 			register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
index 52fcd49df6..87e4cc2f41 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
@@ -71,7 +71,7 @@ chip soc/intel/apollolake
 			register "sata_ports_enable[1]" = "1"
 			register "sata_ports_ssd[0]" = "1"
 			register "sata_ports_ssd[1]" = "1"
-			register "DisableSataSalpSupport" = "1"
+			register "disable_sata_salp_support" = "1"
 			register "sata_speed" = "SATA_GEN2"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
index dc66be63bd..86e92d5289 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
@@ -42,7 +42,7 @@ chip soc/intel/apollolake
 			register "sata_ports_enable[1]" = "1"
 			register "sata_ports_ssd[0]" = "1"
 			register "sata_ports_ssd[1]" = "1"
-			register "DisableSataSalpSupport" = "1"
+			register "disable_sata_salp_support" = "1"
 			register "sata_speed" = "SATA_GEN2"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb
index 0a080c3a63..6cf285f1d8 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb
@@ -58,7 +58,7 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on	# - SATA
-			register "DisableSataSalpSupport" = "1"
+			register "disable_sata_salp_support" = "1"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0
 			register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 5f9b346cc3..44daa5edf9 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -736,7 +736,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 
 	/* SATA config */
 	if (is_devfn_enabled(PCH_DEVFN_SATA)) {
-		silconfig->SataSalpSupport = !(cfg->DisableSataSalpSupport);
+		silconfig->SataSalpSupport = !(cfg->disable_sata_salp_support);
 		ahci_set_speed(cfg->sata_speed);
 		memcpy(silconfig->SataPortsEnable, cfg->sata_ports_enable,
 			sizeof(silconfig->SataPortsEnable));
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 2d6b07929d..d43f3f0292 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -221,7 +221,7 @@ struct soc_intel_apollolake_config {
 	uint8_t disable_xhci_lfps_pm;
 
 	/* SATA Aggressive Link Power Management */
-	uint8_t DisableSataSalpSupport;
+	uint8_t disable_sata_salp_support;
 
 	/* Sata Power Optimisation */
 	uint8_t SataPwrOptimizeDisable;