diff options
| author | Felix Singer <felixsinger@posteo.net> | 2021-07-11 03:53:02 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-07-13 12:42:57 +0000 |
| commit | 989c7c4f8b03ad928483b244337784f6d7463f3f (patch) | |
| tree | b17095372ceb27f804e11a53cc98e1dc6498668a /src/mainboard/siemens/chili/variants | |
| parent | f1cf5ee89339fcf2e49e25d9810d72c18ec7113d (diff) | |
mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOT
Currently, internal flashing is not possible due to FSP lockdown. Thus
let coreboot do chipset lockdown.
Change-Id: Iee4f6986e5edfe1bf6c84fe132bcb47b15bb81f5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56198
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/chili/variants')
| -rw-r--r-- | src/mainboard/siemens/chili/variants/base/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/siemens/chili/variants/chili/devicetree.cb | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index ccbe8047f8..52d8f1ca6a 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -8,6 +8,10 @@ chip soc/intel/cannonlake register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index 4416dbfafa..37a33e7833 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -8,6 +8,10 @@ chip soc/intel/cannonlake register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device cpu_cluster 0 on device lapic 0 on end end |