From 989c7c4f8b03ad928483b244337784f6d7463f3f Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 11 Jul 2021 03:53:02 +0200 Subject: mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, internal flashing is not possible due to FSP lockdown. Thus let coreboot do chipset lockdown. Change-Id: Iee4f6986e5edfe1bf6c84fe132bcb47b15bb81f5 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/56198 Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/siemens/chili/variants/base/devicetree.cb | 4 ++++ src/mainboard/siemens/chili/variants/chili/devicetree.cb | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'src/mainboard/siemens/chili/variants') diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index ccbe8047f8..52d8f1ca6a 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -8,6 +8,10 @@ chip soc/intel/cannonlake register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index 4416dbfafa..37a33e7833 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -8,6 +8,10 @@ chip soc/intel/cannonlake register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device cpu_cluster 0 on device lapic 0 on end end -- cgit v1.2.3