diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-07-08 04:29:39 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-07-12 20:08:01 +0000 |
| commit | 88bc0f1604494de0f87c6954c050e7ef4d1c4457 (patch) | |
| tree | 9492b3a04b2bf7c66ac8202d97b3441d9ccf9306 /src/mainboard/razer/blade_stealth_kbl/devicetree.cb | |
| parent | 702902d71fae63fd35362c82f2a369b42af1a77f (diff) | |
skl/kbl mainboards: Move PCIe related settings into their device scope
Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/razer/blade_stealth_kbl/devicetree.cb')
| -rw-r--r-- | src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index b8ebb1bf57..d38639790c 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -102,17 +102,6 @@ chip soc/intel/skylake .dc_loadline = 310, }" - # Enable Root Ports 3, 5 and 9 - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - - register "PcieRpLtrEnable[2]" = "1" - register "PcieRpLtrEnable[4]" = "1" - register "PcieRpLtrEnable[8]" = "1" - - register "PcieRpHotPlug[4]" = "1" - # PL1 override 25W # PL2 override 44W register "power_limits_config" = "{ @@ -167,8 +156,19 @@ chip soc/intel/skylake device ref heci1 on end device ref uart2 on end device ref pcie_rp1 on end - device ref pcie_rp5 on end - device ref pcie_rp9 on end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" |