From 88bc0f1604494de0f87c6954c050e7ef4d1c4457 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 8 Jul 2024 04:29:39 +0200 Subject: skl/kbl mainboards: Move PCIe related settings into their device scope Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Matt DeVillier Reviewed-by: Erik van den Bogaert Reviewed-by: Jonathon Hall --- .../razer/blade_stealth_kbl/devicetree.cb | 26 +++++++++++----------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'src/mainboard/razer/blade_stealth_kbl/devicetree.cb') diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index b8ebb1bf57..d38639790c 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -102,17 +102,6 @@ chip soc/intel/skylake .dc_loadline = 310, }" - # Enable Root Ports 3, 5 and 9 - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - - register "PcieRpLtrEnable[2]" = "1" - register "PcieRpLtrEnable[4]" = "1" - register "PcieRpLtrEnable[8]" = "1" - - register "PcieRpHotPlug[4]" = "1" - # PL1 override 25W # PL2 override 44W register "power_limits_config" = "{ @@ -167,8 +156,19 @@ chip soc/intel/skylake device ref heci1 on end device ref uart2 on end device ref pcie_rp1 on end - device ref pcie_rp5 on end - device ref pcie_rp9 on end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" -- cgit v1.2.3