diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-03-20 16:14:36 +0100 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-03-25 08:04:17 +0000 |
| commit | c04871a398ca945b42fde0867572094c38f6f92c (patch) | |
| tree | 7cc0bfdfb2fff51929663f0a191f568e99658bbc /src/mainboard/pcengines/apu2/romstage.c | |
| parent | d07ac8ee13ce7f1af5a9d9a5d2e194ab27b8fb9a (diff) | |
mb/pcengines/apu2: add reset logic for PCIe slots
PC Engines apu2 had many problems with PCIe cards detection. The cards
were inconsistently detected when booted from G3, S5 or after a reboot.
AGESA can reset PCIe slots using GPIO via callback. Use it to reset the
slots that support using GPIO as reset signal.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8ff7db6ff85cce45b84729be905e6c895a24f6f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu2/romstage.c')
| -rw-r--r-- | src/mainboard/pcengines/apu2/romstage.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 7565bfca1d..34c42b43ff 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -38,6 +38,15 @@ void board_BeforeAgesa(struct sysinfo *cb) /* Release GPIO32/33 for other uses. */ pm_write8(0xea, 1); + + /* + * Assert resets on the PCIe slots, since AGESA calls deassert callout + * only. Only apu2 uses GPIOs to reset PCIe slots. + */ + if (CONFIG(BOARD_PCENGINES_APU2)) { + gpio1_write8(0xa, gpio1_read8(0xa) & ~(1 << 6)); + gpio1_write8(0xe, gpio1_read8(0xe) & ~(1 << 6)); + } } static void early_lpc_init(void) |