diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-11-09 18:15:51 +0100 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-09-01 13:20:34 +0000 |
| commit | 97112481f508cf031dbb58a0976d2144b6e90873 (patch) | |
| tree | 66a779c050633258c46d390e89b44a9580004437 /src/mainboard/msi/ms7d25/devicetree.cb | |
| parent | 69cef8e6942ab62abc02062522f62cc1bb337f55 (diff) | |
mb/msi/ms7d25: Configure ASPM and Clock PM based on Kconfig
Add support for FSP ASPM and Clock PM configuration based on Kconfig
options: PCIEXP_ASPM, PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE. For some
use cases it may be desirable to disable ASPM and Clock PM to achieve
more deterministic and higher performance of PCIe devices.
TEST=Boot MSI PRO Z690-A DDR4 without ASPM and Clock PM. Confirm all
PCIe devices are still working and ASPM and Clock PM capabilities
are not present on the PCIe Root Ports.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6d9d11016bed89dcfee6909d0d3e3e2e56237a2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69825
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/msi/ms7d25/devicetree.cb')
| -rw-r--r-- | src/mainboard/msi/ms7d25/devicetree.cb | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index c76b01bfa1..f0c8d2d287 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -99,8 +99,6 @@ chip soc/intel/alderlake .clk_src = 0, .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong" "PCI_E1" "SlotDataBusWidth16X" @@ -112,8 +110,6 @@ chip soc/intel/alderlake .clk_src = 9, .clk_req = 9, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X" @@ -142,8 +138,6 @@ chip soc/intel/alderlake .clk_src = 10, .clk_req = 10, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" "PCI_E2" "SlotDataBusWidth1X" @@ -153,8 +147,6 @@ chip soc/intel/alderlake .clk_src = 17, .clk_req = 17, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCI_E4" "SlotDataBusWidth1X" @@ -164,8 +156,6 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 12, .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" end device ref pcie_rp4 off end @@ -175,8 +165,6 @@ chip soc/intel/alderlake .clk_src = 15, .clk_req = 15, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCI_E3" "SlotDataBusWidth4X" @@ -187,8 +175,6 @@ chip soc/intel/alderlake .clk_src = 13, .clk_req = 13, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_3" "SlotDataBusWidth4X" @@ -211,8 +197,6 @@ chip soc/intel/alderlake .clk_src = 14, .clk_req = 14, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_4" "SlotDataBusWidth4X" @@ -223,8 +207,6 @@ chip soc/intel/alderlake .clk_src = 8, .clk_req = 8, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_2" "SlotDataBusWidth4X" |