mb/msi/ms7d25: Configure ASPM and Clock PM based on Kconfig

Add support for FSP ASPM and Clock PM configuration based on Kconfig
options: PCIEXP_ASPM, PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE. For some
use cases it may be desirable to disable ASPM and Clock PM to achieve
more deterministic and higher performance of PCIe devices.

TEST=Boot MSI PRO Z690-A DDR4 without ASPM and Clock PM. Confirm all
PCIe devices are still working and ASPM and Clock PM capabilities
are not present on the PCIe Root Ports.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6d9d11016bed89dcfee6909d0d3e3e2e56237a2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69825
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 188 insertions, 40 deletions

diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb
index c76b01bfa1..f0c8d2d287 100644
--- a/src/mainboard/msi/ms7d25/devicetree.cb
+++ b/src/mainboard/msi/ms7d25/devicetree.cb
@@ -99,8 +99,6 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.clk_req = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-				.PcieRpL1Substates = L1_SS_L1_2,
-				.pcie_rp_aspm = ASPM_L0S_L1,
 			}"
 			smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong"
 					 "PCI_E1" "SlotDataBusWidth16X"
@@ -112,8 +110,6 @@ chip soc/intel/alderlake
 				.clk_src = 9,
 				.clk_req = 9,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-				.PcieRpL1Substates = L1_SS_L1_2,
-				.pcie_rp_aspm = ASPM_L0S_L1,
 			}"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
 					 "M2_1" "SlotDataBusWidth4X"
@@ -142,8 +138,6 @@ chip soc/intel/alderlake
 				.clk_src = 10,
 				.clk_req = 10,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-				.PcieRpL1Substates = L1_SS_L1_2,
-				.pcie_rp_aspm = ASPM_L0S_L1,
 			}"
 			smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort"
 					 "PCI_E2" "SlotDataBusWidth1X"
@@ -153,8 +147,6 @@ chip soc/intel/alderlake
 				.clk_src = 17,
 				.clk_req = 17,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-				.PcieRpL1Substates = L1_SS_L1_2,
-				.pcie_rp_aspm = ASPM_L0S_L1,
 			}"
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
 					 "PCI_E4" "SlotDataBusWidth1X"
@@ -164,8 +156,6 @@ chip soc/intel/alderlake
 			register "pch_pcie_rp[PCH_RP(3)]" = "{
 				.clk_src = 12,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
-				.PcieRpL1Substates = L1_SS_L1_2,
-				.pcie_rp_aspm = ASPM_L0S_L1,
 			}"
 		end
 		device ref pcie_rp4 off end
@@ -175,8 +165,6 @@ chip soc/intel/alderlake
 				.clk_src = 15,
 				.clk_req = 15,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-				.PcieRpL1Substates = L1_SS_L1_2,
-				.pcie_rp_aspm = ASPM_L0S_L1,
 			}"
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
 					 "PCI_E3" "SlotDataBusWidth4X"
@@ -187,8 +175,6 @@ chip soc/intel/alderlake
 				.clk_src = 13,
 				.clk_req = 13,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-				.PcieRpL1Substates = L1_SS_L1_2,
-				.pcie_rp_aspm = ASPM_L0S_L1,
 			}"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
 					 "M2_3" "SlotDataBusWidth4X"
@@ -211,8 +197,6 @@ chip soc/intel/alderlake
 				.clk_src = 14,
 				.clk_req = 14,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-				.PcieRpL1Substates = L1_SS_L1_2,
-				.pcie_rp_aspm = ASPM_L0S_L1,
 			}"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
 					 "M2_4" "SlotDataBusWidth4X"
@@ -223,8 +207,6 @@ chip soc/intel/alderlake
 				.clk_src = 8,
 				.clk_req = 8,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-				.PcieRpL1Substates = L1_SS_L1_2,
-				.pcie_rp_aspm = ASPM_L0S_L1,
 			}"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
 					 "M2_2" "SlotDataBusWidth4X"
diff --git a/src/mainboard/msi/ms7d25/gpio.h b/src/mainboard/msi/ms7d25/gpio.h
index 210c43d398..62625c0d50 100644
--- a/src/mainboard/msi/ms7d25/gpio.h
+++ b/src/mainboard/msi/ms7d25/gpio.h
@@ -699,3 +699,110 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_D23 - GPIO */
 	PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI),
 };
+
+/* PCIe CLK REQs as per devicetree.cb */
+static const struct pad_config clkreq_disabled_table[] = {
+	/* GPP_J9 - SRCCLKREQ17# */
+	PAD_NC(GPP_J9, NONE),
+	/* GPP_H2 - SRCCLKREQ8# */
+	PAD_NC(GPP_H2, NONE),
+	/* GPP_H3 - SRCCLKREQ9# */
+	PAD_NC(GPP_H3, NONE),
+	/* GPP_H4 - SRCCLKREQ10# */
+	PAD_NC(GPP_H4, NONE),
+	/* GPP_H6 - SRCCLKREQ12# */
+	PAD_NC(GPP_H6, NONE),
+	/* GPP_H7 - SRCCLKREQ13# */
+	PAD_NC(GPP_H7, NONE),
+	/* GPP_H8 - SRCCLKREQ14# */
+	PAD_NC(GPP_H8, NONE),
+	/* GPP_H9 - SRCCLKREQ15# */
+	PAD_NC(GPP_H9, NONE),
+	/* GPP_D0 - SRCCLKREQ0# */
+	PAD_NC(GPP_D0, NONE),
+
+	/* CPU PCIe CLKREQ virtual wire message buses */
+	_PAD_CFG_STRUCT(VGPIO_PCIE_0,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_1,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_2,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_3,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_4,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_5,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_6,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_7,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_8,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_9,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+
+	_PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+
+	_PAD_CFG_STRUCT(VGPIO_PCIE_32, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_33, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_34, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_35, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_36, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_37, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_38, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_39, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_40, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_41, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_42, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_43, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_44, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_45, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_46, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_47, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_72, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_73, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_74, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_75, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+
+	_PAD_CFG_STRUCT(VGPIO_PCIE_48, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_49, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_50, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_51, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_52, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_53, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_54, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_55, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_56, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_57, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_58, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_59, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_60, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_61, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_62, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_63, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_76, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_77, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_78, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_79, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+};
diff --git a/src/mainboard/msi/ms7d25/mainboard.c b/src/mainboard/msi/ms7d25/mainboard.c
index 7e865331ef..f1244491e3 100644
--- a/src/mainboard/msi/ms7d25/mainboard.c
+++ b/src/mainboard/msi/ms7d25/mainboard.c
@@ -66,6 +66,21 @@ const char *smbios_system_sku(void)
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
+	uint8_t aspm, aspm_l1;
+
+	/* ASPM L1 sub-states require CLKREQ, so CLK_PM should be enabled as well */
+	if (CONFIG(PCIEXP_L1_SUB_STATE) && CONFIG(PCIEXP_CLK_PM))
+		aspm_l1 = 2; // 2 - L1.1 and L1.2
+	else
+		aspm_l1 = 0;
+
+	if (CONFIG(PCIEXP_ASPM)) {
+		aspm = CONFIG(PCIEXP_L1_SUB_STATE) ? 3 : 1; // 3 - L0sL1, 1 - L0s
+	} else {
+		aspm = 0;
+		aspm_l1 = 0;
+	}
+
 	memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm));
 	memset(params->CpuPcieRpEnableCpm, 0, sizeof(params->CpuPcieRpEnableCpm));
 	memset(params->CpuPcieClockGating, 0, sizeof(params->CpuPcieClockGating));
@@ -91,13 +106,13 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->PcieRpPmSci[20]   = 1; // M2_4
 	params->PcieRpPmSci[24]   = 1; // M2_2
 
-	params->PcieRpMaxPayload[0]    = 1; // PCI_E2
-	params->PcieRpMaxPayload[1]    = 1; // PCI_E4
-	params->PcieRpMaxPayload[2]    = 1; // Ethernet
-	params->PcieRpMaxPayload[4]    = 1; // PCI_E3
-	params->PcieRpMaxPayload[8]    = 1; // M2_3
-	params->PcieRpMaxPayload[20]   = 1; // M2_4
-	params->PcieRpMaxPayload[24]   = 1; // M2_2
+	params->PcieRpMaxPayload[0]  = 1; // PCI_E2
+	params->PcieRpMaxPayload[1]  = 1; // PCI_E4
+	params->PcieRpMaxPayload[2]  = 1; // Ethernet
+	params->PcieRpMaxPayload[4]  = 1; // PCI_E3
+	params->PcieRpMaxPayload[8]  = 1; // M2_3
+	params->PcieRpMaxPayload[20] = 1; // M2_4
+	params->PcieRpMaxPayload[24] = 1; // M2_2
 
 	params->CpuPcieRpTransmitterHalfSwing[0] = 1; // M2_1
 	params->CpuPcieRpTransmitterHalfSwing[1] = 1; // PCI_E1
@@ -109,12 +124,32 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->PcieRpTransmitterHalfSwing[20]   = 1; // M2_4
 	params->PcieRpTransmitterHalfSwing[24]   = 1; // M2_2
 
-	params->PcieRpEnableCpm[0]  = 1; // PCI_E2
-	params->PcieRpEnableCpm[1]  = 1; // PCI_E4
-	params->PcieRpEnableCpm[4]  = 1; // PCI_E3
-	params->PcieRpEnableCpm[8]  = 1; // M2_3
-	params->PcieRpEnableCpm[20] = 1; // M2_4
-	params->PcieRpEnableCpm[24] = 1; // M2_2
+	params->CpuPcieRpEnableCpm[0] = CONFIG(PCIEXP_CLK_PM); // M2_1
+	params->CpuPcieRpEnableCpm[1] = CONFIG(PCIEXP_CLK_PM); // PCI_E1
+	params->PcieRpEnableCpm[0]    = CONFIG(PCIEXP_CLK_PM); // PCI_E2
+	params->PcieRpEnableCpm[1]    = CONFIG(PCIEXP_CLK_PM); // PCI_E4
+	params->PcieRpEnableCpm[4]    = CONFIG(PCIEXP_CLK_PM); // PCI_E3
+	params->PcieRpEnableCpm[8]    = CONFIG(PCIEXP_CLK_PM); // M2_3
+	params->PcieRpEnableCpm[20]   = CONFIG(PCIEXP_CLK_PM); // M2_4
+	params->PcieRpEnableCpm[24]   = CONFIG(PCIEXP_CLK_PM); // M2_2
+
+	params->CpuPcieRpL1Substates[0] = aspm_l1; // M2_1
+	params->CpuPcieRpL1Substates[1] = aspm_l1; // PCI_E1
+	params->PcieRpL1Substates[0]    = aspm_l1; // PCI_E2
+	params->PcieRpL1Substates[1]    = aspm_l1; // PCI_E4
+	params->PcieRpL1Substates[4]    = aspm_l1; // PCI_E3
+	params->PcieRpL1Substates[8]    = aspm_l1; // M2_3
+	params->PcieRpL1Substates[20]   = aspm_l1; // M2_4
+	params->PcieRpL1Substates[24]   = aspm_l1; // M2_2
+
+	params->CpuPcieRpAspm[0] = aspm; // M2_1
+	params->CpuPcieRpAspm[1] = aspm; // PCI_E1
+	params->PcieRpAspm[0]    = aspm; // PCI_E2
+	params->PcieRpAspm[1]    = aspm; // PCI_E4
+	params->PcieRpAspm[4]    = aspm; // PCI_E3
+	params->PcieRpAspm[8]    = aspm; // M2_3
+	params->PcieRpAspm[20]   = aspm; // M2_4
+	params->PcieRpAspm[24]   = aspm; // M2_2
 
 	params->PcieRpAcsEnabled[0]  = 1; // PCI_E2
 	params->PcieRpAcsEnabled[1]  = 1; // PCI_E4
@@ -124,17 +159,15 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->PcieRpAcsEnabled[20] = 1; // M2_4
 	params->PcieRpAcsEnabled[24] = 1; // M2_2
 
-	params->CpuPcieRpEnableCpm[0] = 1; // M2_1
-	params->CpuPcieClockGating[0] = 1;
-	params->CpuPciePowerGating[0] = 1;
+	params->CpuPcieClockGating[0] = CONFIG(PCIEXP_CLK_PM);
+	params->CpuPciePowerGating[0] = CONFIG(PCIEXP_CLK_PM);
 	params->CpuPcieRpMultiVcEnabled[0] = 1;
 	params->CpuPcieRpPeerToPeerMode[0] = 1;
 	params->CpuPcieRpMaxPayload[0] = 2; // 512B
 	params->CpuPcieRpAcsEnabled[0] = 1;
 
-	params->CpuPcieRpEnableCpm[1] = 1; // PCI_E1
-	params->CpuPcieClockGating[1] = 1;
-	params->CpuPciePowerGating[1] = 1;
+	params->CpuPcieClockGating[1] = CONFIG(PCIEXP_CLK_PM);
+	params->CpuPciePowerGating[1] = CONFIG(PCIEXP_CLK_PM);
 	params->CpuPcieRpPeerToPeerMode[1] = 1;
 	params->CpuPcieRpMaxPayload[1] = 2; // 512B
 	params->CpuPcieRpAcsEnabled[1] = 1;
diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c
index 833ff1ac97..3ced7f812f 100644
--- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c
+++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c
@@ -5,9 +5,13 @@
 #include <fsp/api.h>
 #include <soc/romstage.h>
 #include <soc/meminit.h>
+#include <string.h>
 
 #include "gpio.h"
 
+#define FSP_CLK_NOTUSED			0xFF
+#define FSP_CLK_FREE_RUNNING		0x80
+
 static const struct mb_cfg ddr4_mem_config = {
 	.type = MEM_TYPE_DDR4,
 	/* According to DOC #573387 rcomp values no longer have to be provided */
@@ -49,11 +53,30 @@ static const struct mem_spd dimm_module_spd_info = {
 	},
 };
 
+static void disable_pcie_clock_requests(FSP_M_CONFIG *m_cfg)
+{
+	memset(m_cfg->PcieClkSrcUsage, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcUsage));
+	memset(m_cfg->PcieClkSrcClkReq, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcClkReq));
+
+	/* PCIe CLK SRCes as per devicetree.cb */
+	m_cfg->PcieClkSrcUsage[0]  = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[8]  = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[9]  = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[10] = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[12] = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[13] = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[14] = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[15] = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[17] = FSP_CLK_FREE_RUNNING;
+
+	gpio_configure_pads(clkreq_disabled_table, ARRAY_SIZE(clkreq_disabled_table));
+}
+
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
-	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 1;
-	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = 1;
-	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = 0;
+	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = CONFIG(PCIEXP_CLK_PM);
+	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = CONFIG(PCIEXP_CLK_PM);
+	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = CONFIG(PCIEXP_CLK_PM);
 	memupd->FspmConfig.DmiMaxLinkSpeed = 4; // Gen4 speed, undocumented
 	memupd->FspmConfig.DmiAspm = 0;
 	memupd->FspmConfig.DmiAspmCtrl = 0;
@@ -67,4 +90,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 		memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false);
 
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+
+	if (!CONFIG(PCIEXP_CLK_PM))
+		disable_pcie_clock_requests(&memupd->FspmConfig);
 }