diff options
| author | Martin Roth <martin@coreboot.org> | 2021-10-01 14:37:30 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-10-05 18:06:52 +0000 |
| commit | 50863daef8ed75c0cb3dfd375e7622c898de5821 (patch) | |
| tree | cbb2dea518524f8c9ce5edca5d57132ca9705086 /src/mainboard/lippert | |
| parent | 0949e739066c3509e05db2b9ed71cefaaa62205f (diff) | |
src/mainboard to src/security: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/lippert')
| -rw-r--r-- | src/mainboard/lippert/frontrunner-af/dsdt.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 5d1e2613ba..e35a70b8ae 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -535,7 +535,7 @@ DefinitionBlock ( * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ |