mb/*: Update SPD mapping for sandybridge boards

Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.

Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.

Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

31 files changed, 46 insertions, 163 deletions

diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb
index dd431dfda4..ead7e0bb87 100644
--- a/src/mainboard/lenovo/l520/devicetree.cb
+++ b/src/mainboard/lenovo/l520/devicetree.cb
@@ -11,6 +11,7 @@ chip northbridge/intel/sandybridge
 	register "gpu_panel_power_down_delay" = "0"
 	register "gpu_panel_power_up_delay" = "0"
 	register "gpu_pch_backlight" = "0x00000000"
+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
 
 	device domain 0 on
 		subsystemid 0x17aa 0x21dd inherit
diff --git a/src/mainboard/lenovo/l520/early_init.c b/src/mainboard/lenovo/l520/early_init.c
index b6202c735a..ebcd639e6a 100644
--- a/src/mainboard/lenovo/l520/early_init.c
+++ b/src/mainboard/lenovo/l520/early_init.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
 
@@ -20,9 +19,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
 	{ 1, 0, -1 },
 };
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x52, id_only);
-}
diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c
index 434b58c6a3..58e95932b8 100644
--- a/src/mainboard/lenovo/s230u/early_init.c
+++ b/src/mainboard/lenovo/s230u/early_init.c
@@ -1,17 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <stdint.h>
-#include <string.h>
-#include <cbfs.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
 #include "ec.h"
 
-#define SPD_LEN 256
-
 void mainboard_pch_lpc_setup(void)
 {
 	/* Memory map KB9012 EC registers */
@@ -54,26 +49,27 @@ static const char *mainboard_spd_names[9] = {
 	"HYNIX 2GB",
 };
 
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+static unsigned int get_spd_index(void)
 {
-	void *spd_file;
-	size_t spd_file_len = 0;
 	const int spd_gpios[] = {71, 70, 16, 48, -1};
 
-	u32 spd_index = get_gpios(spd_gpios);
+	unsigned int spd_index = get_gpios(spd_gpios);
 	if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) {
 		/* Fallback to pessimistic 2GB image (ELPIDA 2GB) */
 		spd_index = 6;
 	}
 
+	return spd_index;
+}
+
+void mb_get_spd_map(struct spd_info *spdi)
+{
+	unsigned int spd_index = get_spd_index();
+
 	printk(BIOS_INFO, "SPD index %d (%s)\n",
 		spd_index, mainboard_spd_names[spd_index]);
 
 	/* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */
-	spd_file = cbfs_map("spd.bin", &spd_file_len);
-
-	if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN)
-		die("SPD data not found.");
-
-	memcpy(spd, spd_file + SPD_LEN * spd_index, SPD_LEN);
+	spdi->addresses[0] = SPD_MEMORY_DOWN;
+	spdi->spd_index = spd_index;
 }
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
index 953044a5d2..d4b31afe88 100644
--- a/src/mainboard/lenovo/t420/devicetree.cb
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -15,6 +15,8 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x06100610"
 
+	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
+
 	device domain 0 on
 		subsystemid 0x17aa 0x21ce inherit
 
diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c
index 1be50fd6ed..c90221ed67 100644
--- a/src/mainboard/lenovo/t420/early_init.c
+++ b/src/mainboard/lenovo/t420/early_init.c
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/pci_ops.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
-#include <device/device.h>
 
 static void hybrid_graphics_init(void)
 {
@@ -51,12 +49,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, -1 }, /* P13: camera (LCD), no OC */
 };
 
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x51, id_only);
-}
-
 void mainboard_early_init(int s3resume)
 {
 	hybrid_graphics_init();
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index fc3b12c1dd..fb309170fe 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -15,6 +15,8 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x06100610"
 
+	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
+
 	device domain 0 on
 		subsystemid 0x17aa 0x21d2 inherit
 
diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c
index 990a0b3e52..e5e95b218a 100644
--- a/src/mainboard/lenovo/t420s/early_init.c
+++ b/src/mainboard/lenovo/t420s/early_init.c
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/pci_ops.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
-#include <device/device.h>
 
 static void hybrid_graphics_init(void)
 {
@@ -50,12 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, -1 }, /* P13: camera (LCD), no OC */
 };
 
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x51, id_only);
-}
-
 void mainboard_early_init(int s3resume)
 {
 	hybrid_graphics_init();
diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb
index 73fd5b20cc..6492542906 100644
--- a/src/mainboard/lenovo/t430/devicetree.cb
+++ b/src/mainboard/lenovo/t430/devicetree.cb
@@ -14,6 +14,8 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x11551155"
 
+	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
+
 	device domain 0 on
 		subsystemid 0x17aa 0x21f3 inherit
 
diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c
index baafb5032a..5e397ab7c4 100644
--- a/src/mainboard/lenovo/t430/early_init.c
+++ b/src/mainboard/lenovo/t430/early_init.c
@@ -2,12 +2,10 @@
 
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/lenovo/pmh7/pmh7.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
-#include <device/device.h>
 
 static void hybrid_graphics_init(void)
 {
@@ -57,9 +55,3 @@ void mainboard_early_init(int s3resume)
 {
 	hybrid_graphics_init();
 }
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x51, id_only);
-}
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
index 4250665e2c..698460b1dc 100644
--- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
+++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
@@ -1,4 +1,5 @@
 chip northbridge/intel/sandybridge
+	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
 	device domain 0 on
 		chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
 			# Enable hotplug on Port 5 for Thunderbolt controller
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
index c6414863ce..8980572174 100644
--- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
@@ -3,7 +3,7 @@
 #include <option.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/lenovo/pmh7/pmh7.h>
 #include <types.h>
@@ -25,12 +25,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, -1 }, /* P13: camera, no OC */
 };
 
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x51, id_only);
-}
-
 void mainboard_early_init(int s3resume)
 {
 	u8 enable_peg = get_uint_option("enable_dual_graphics", 0);
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c
index 54236a1ffc..6fbbaadbf4 100644
--- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c
+++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c
@@ -1,11 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <console/console.h>
-#include <cbfs.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
-#include <string.h>
+#include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <ec/lenovo/pmh7/pmh7.h>
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },  /* SSP1: right */
@@ -24,15 +20,10 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, -1 }, /* B1P6: Camera */
 };
 
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+void mb_get_spd_map(struct spd_info *spdi)
 {
 	/* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */
-	size_t spd_file_len = 0;
-	void *spd_file = cbfs_map("spd.bin", &spd_file_len);
-
-	if (!spd_file || spd_file_len < sizeof(spd_raw_data))
-		die("SPD data for C1S0 not found.");
-
-	memcpy(&spd[0], spd_file, spd_file_len);
-	read_spd(&spd[2], 0x51, id_only);
+	spdi->addresses[0] = SPD_MEMORY_DOWN;
+	spdi->addresses[2] = 0x51;
+	spdi->spd_index = 0;
 }
diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc
index a3b838ba10..69ef08873b 100644
--- a/src/mainboard/lenovo/t520/Makefile.inc
+++ b/src/mainboard/lenovo/t520/Makefile.inc
@@ -2,7 +2,6 @@
 
 bootblock-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
-romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 bootblock-y += early_init.c
 romstage-y += early_init.c
diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c
index 54d42ea3dc..219ffc1751 100644
--- a/src/mainboard/lenovo/t520/early_init.c
+++ b/src/mainboard/lenovo/t520/early_init.c
@@ -4,7 +4,6 @@
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include <device/device.h>
diff --git a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb
index b976d6d904..d1634f81d6 100644
--- a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb
+++ b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb
@@ -1,4 +1,5 @@
 chip northbridge/intel/sandybridge
+	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
 	device domain 0 on
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
 			device pci 1f.0 on # LPC bridge
diff --git a/src/mainboard/lenovo/t520/variants/t520/romstage.c b/src/mainboard/lenovo/t520/variants/t520/romstage.c
deleted file mode 100644
index cf5b18d4f2..0000000000
--- a/src/mainboard/lenovo/t520/variants/t520/romstage.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <northbridge/intel/sandybridge/raminit_native.h>
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x51, id_only);
-}
diff --git a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb
index 3e1c90ee63..4e03e753f4 100644
--- a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb
+++ b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb
@@ -1,4 +1,5 @@
 chip northbridge/intel/sandybridge
+	register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}"
 	device domain 0 on
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
 			device pci 1c.6 on end # PCIe Port #7 USB 3.0
diff --git a/src/mainboard/lenovo/t520/variants/w520/romstage.c b/src/mainboard/lenovo/t520/variants/w520/romstage.c
deleted file mode 100644
index 493a0a05ff..0000000000
--- a/src/mainboard/lenovo/t520/variants/w520/romstage.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <northbridge/intel/sandybridge/raminit_native.h>
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[1], 0x52, id_only);
-	read_spd(&spd[2], 0x51, id_only);
-	read_spd(&spd[3], 0x53, id_only);
-}
diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb
index 78f7b9b34c..98551ac968 100644
--- a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb
+++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb
@@ -1,4 +1,5 @@
 chip northbridge/intel/sandybridge
+	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
 	device domain 0 on
 		chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
 			device pci 1f.0 on # PCI-LPC bridge
diff --git a/src/mainboard/lenovo/t530/variants/t530/romstage.c b/src/mainboard/lenovo/t530/variants/t530/romstage.c
index 22bf0764aa..2290bcea13 100644
--- a/src/mainboard/lenovo/t530/variants/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/variants/t530/romstage.c
@@ -1,14 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x51, id_only);
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1,  0 }, /* P0: USB double port upper, USB3, OC 0 */
 	{ 1, 1,  1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */
diff --git a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb
index 115bc1f12a..77b75fd237 100644
--- a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb
+++ b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb
@@ -1,4 +1,5 @@
 chip northbridge/intel/sandybridge
+	register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}"
 	device domain 0 on
 		device pci 02.0 on # Internal graphics VGA controller
 			subsystemid 0x17aa 0x21f5
diff --git a/src/mainboard/lenovo/t530/variants/w530/romstage.c b/src/mainboard/lenovo/t530/variants/w530/romstage.c
index f3ccc14266..7458d1ad4d 100644
--- a/src/mainboard/lenovo/t530/variants/w530/romstage.c
+++ b/src/mainboard/lenovo/t530/variants/w530/romstage.c
@@ -1,16 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[1], 0x52, id_only);
-	read_spd(&spd[2], 0x51, id_only);
-	read_spd(&spd[3], 0x53, id_only);
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1,  0 }, /* P0: USB double port upper, USB3, OC 0 */
 	{ 1, 1,  1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */
diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb
index beb26095d4..96385ed2cd 100644
--- a/src/mainboard/lenovo/x131e/devicetree.cb
+++ b/src/mainboard/lenovo/x131e/devicetree.cb
@@ -14,6 +14,8 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x11551155"
 
+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
 	device domain 0 on
 		subsystemid 0x17aa 0x21fe inherit
 
diff --git a/src/mainboard/lenovo/x131e/early_init.c b/src/mainboard/lenovo/x131e/early_init.c
index 9ace77820b..410dea6aff 100644
--- a/src/mainboard/lenovo/x131e/early_init.c
+++ b/src/mainboard/lenovo/x131e/early_init.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
@@ -19,9 +18,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{0, 0, 0},
 	{1, 0, -1},	/* P13: Bluetooth (no OC) */
 };
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x52, id_only);
-}
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
index 6f18feee91..00d94e69ab 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
@@ -1,12 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <stdint.h>
 #include <string.h>
 #include <console/console.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <cbfs.h>
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	/* enabled, current, OC pin */
@@ -26,27 +24,10 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, -1 },/* P13 Camera */
 };
 
-static uint8_t *get_spd_data(int spd_index)
+static unsigned int get_spd_index(void)
 {
-	uint8_t *spd_file;
-	size_t spd_file_len;
-
-	printk(BIOS_DEBUG, "spd index %d\n", spd_index);
-	spd_file = cbfs_map("spd.bin", &spd_file_len);
-	if (!spd_file)
-		die("SPD data not found.");
-
-	if (spd_file_len < spd_index * 256)
-		die("Missing SPD data.");
-
-	return spd_file + spd_index * 256;
-}
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	uint8_t *memory;
 	const int spd_gpio_vector[] = {25, 45, -1};
-	int spd_index = get_gpios(spd_gpio_vector);
+	unsigned int spd_index = get_gpios(spd_gpio_vector);
 
 	/* 4gb model = 0, 8gb model = 1 */
 	/* int extended_memory_version = get_gpio(44); */
@@ -69,7 +50,12 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	if (spd_index == 3)
 		die("Unsupported Memory. (detected 'reserved' memory configuration).");
 
-	memory = get_spd_data(spd_index);
-	memcpy(&spd[0], memory, 256);
-	memcpy(&spd[2], memory, 256);
+	return spd_index;
+}
+
+void mb_get_spd_map(struct spd_info *spdi)
+{
+	spdi->addresses[0] = SPD_MEMORY_DOWN;
+	spdi->addresses[2] = SPD_MEMORY_DOWN;
+	spdi->spd_index = get_spd_index();
 }
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 049eea6d84..b6736d2412 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x06100610"
 
+	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
 	register "ec_present" = "1"		# I have an embedded controller
 	register "max_mem_clock_mhz" = "666"	# So DDR3 freq = 1333
 
diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c
index 8edb0dd735..f969b4feb3 100644
--- a/src/mainboard/lenovo/x220/early_init.c
+++ b/src/mainboard/lenovo/x220/early_init.c
@@ -1,21 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/hpet.h>
 #include <stdint.h>
 #include <northbridge/intel/sandybridge/raminit.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	const uint8_t spdaddr[] = {0xa0, 0x00, 0xa2, 0x00};
-
-	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
-}
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x51, id_only);
 }
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index fdd5059e6a..52a2e70a22 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x11551155"
 
+	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
 	device domain 0 on
 		subsystemid 0x17aa 0x21fa inherit
 
diff --git a/src/mainboard/lenovo/x230/variants/x230/early_init.c b/src/mainboard/lenovo/x230/variants/x230/early_init.c
index 5fe81791de..7084e9a0b0 100644
--- a/src/mainboard/lenovo/x230/variants/x230/early_init.c
+++ b/src/mainboard/lenovo/x230/variants/x230/early_init.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
 
@@ -20,9 +19,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, -1 }, /* P12: wlan, no OC */
 	{ 1, 1, -1 }, /* P13: webcam, no OC */
 };
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x51, id_only);
-}
diff --git a/src/mainboard/lenovo/x230/variants/x230s/early_init.c b/src/mainboard/lenovo/x230/variants/x230s/early_init.c
index 362e7fa64a..16d11a37ce 100644
--- a/src/mainboard/lenovo/x230/variants/x230s/early_init.c
+++ b/src/mainboard/lenovo/x230/variants/x230s/early_init.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
@@ -19,8 +18,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{1, 3, -1}, /* B1P5: WLAN USB */
 	{1, 1, -1}, /* B1P6: Camera */
 };
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-}
diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb
index 1c0efd346b..9d020e31ce 100644
--- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb
+++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb
@@ -11,6 +11,7 @@ chip northbridge/intel/sandybridge
 	register "gpu_panel_power_down_delay" = "500"		# 50ms
 	register "gpu_panel_power_up_delay" = "2000"		# 200ms
 
+	register "spd_addresses" = "{0x50, 0, 0, 0}"
 	device domain 0 on
 		subsystemid 0x17aa 0x2209 inherit
 		chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH