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authorArthur Heymans <arthur@aheymans.xyz>2022-11-07 10:03:40 +0100
committerArthur Heymans <arthur@aheymans.xyz>2022-12-01 10:28:03 +0000
commit22d6ee8d9cda51d20ca4173593b9574f7dac65ff (patch)
tree9b672418bce3536132eceff8a288d0ef7340e1ed /src/mainboard/lenovo
parent2fb6f68ef09358aa6f2550519e71a1d74702d5ef (diff)
nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree
Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo')
-rw-r--r--src/mainboard/lenovo/t60/devicetree.cb2
-rw-r--r--src/mainboard/lenovo/x60/devicetree.cb2
2 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index 7709a87949..c77af6bb26 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -14,6 +14,7 @@ chip northbridge/intel/i945
register "gpu_panel_power_cycle_delay" = "2"
device cpu_cluster 0 on
+ ops i945_cpu_bus_ops
chip cpu/intel/socket_m
device lapic 0 on end
end
@@ -22,6 +23,7 @@ chip northbridge/intel/i945
register "pci_mmio_size" = "768"
device domain 0 on
+ ops i945_pci_domain_ops
device pci 00.0 on # Host bridge
subsystemid 0x17aa 0x2015
end
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index 8620062928..d56ec514aa 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -14,6 +14,7 @@ chip northbridge/intel/i945
register "gpu_panel_power_cycle_delay" = "2"
device cpu_cluster 0 on
+ ops i945_cpu_bus_ops
chip cpu/intel/socket_m
device lapic 0 on end
end
@@ -22,6 +23,7 @@ chip northbridge/intel/i945
register "pci_mmio_size" = "768"
device domain 0 on
+ ops i945_pci_domain_ops
device pci 00.0 on # Host bridge
subsystemid 0x17aa 0x2017
end