From 22d6ee8d9cda51d20ca4173593b9574f7dac65ff Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 7 Nov 2022 10:03:40 +0100 Subject: nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t60/devicetree.cb | 2 ++ src/mainboard/lenovo/x60/devicetree.cb | 2 ++ 2 files changed, 4 insertions(+) (limited to 'src/mainboard/lenovo') diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 7709a87949..c77af6bb26 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -14,6 +14,7 @@ chip northbridge/intel/i945 register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_m device lapic 0 on end end @@ -22,6 +23,7 @@ chip northbridge/intel/i945 register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2015 end diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 8620062928..d56ec514aa 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -14,6 +14,7 @@ chip northbridge/intel/i945 register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_m device lapic 0 on end end @@ -22,6 +23,7 @@ chip northbridge/intel/i945 register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2017 end -- cgit v1.2.3