mainboard/lenovo/g505s: New port Richland APU A10-5750M

Richland APU A10-5750M
8GB RAM
4MB Flash

Boots to working Linux with SeaBIOS payload. S3 works with
Linux 3.16.3-2 Debian Jessie.

Change-Id: I5d05d1b31400fdb9e41c2e011c5b0bf9986fe970
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7560
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 25 insertions, 0 deletions

diff --git a/src/mainboard/lenovo/g505s/mainboard.h b/src/mainboard/lenovo/g505s/mainboard.h
new file mode 100644
index 0000000000..6131df2378
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/mainboard.h
@@ -0,0 +1,25 @@
+/*
+ * "The way things are connected" and a few setup options
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#ifndef _MAINBOARD_LENOVO_G505S_MAINBOARD_H
+#define _MAINBOARD_LENOVO_G505S_MAINBOARD_H
+
+/* What is connected to GEVENT pins */
+#define EC_SCI_GEVENT		3
+#define EC_LID_GEVENT		22
+#define EC_SMI_GEVENT		23
+#define PCIE_GEVENT		8
+
+/* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but
+ * we make the distinction between GEVENT pin and SCI.
+ */
+#define EC_SCI_GPE 		EC_SCI_GEVENT
+#define EC_LID_GPE		EC_LID_GEVENT
+#define PME_GPE			0x0b
+#define PCIE_GPE		0x18
+
+#endif /* _MAINBOARD_LENOVO_G505S_MAINBOARD_H   */