From 32960e30f08f678355b20b5702e8028351a7275e Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Sun, 23 Nov 2014 17:38:52 +1100 Subject: mainboard/lenovo/g505s: New port Richland APU A10-5750M MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Richland APU A10-5750M 8GB RAM 4MB Flash Boots to working Linux with SeaBIOS payload. S3 works with Linux 3.16.3-2 Debian Jessie. Change-Id: I5d05d1b31400fdb9e41c2e011c5b0bf9986fe970 Signed-off-by: Edward O'Callaghan Signed-off-by: Damien Zammit Reviewed-on: http://review.coreboot.org/7560 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/lenovo/g505s/mainboard.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 src/mainboard/lenovo/g505s/mainboard.h (limited to 'src/mainboard/lenovo/g505s/mainboard.h') diff --git a/src/mainboard/lenovo/g505s/mainboard.h b/src/mainboard/lenovo/g505s/mainboard.h new file mode 100644 index 0000000000..6131df2378 --- /dev/null +++ b/src/mainboard/lenovo/g505s/mainboard.h @@ -0,0 +1,25 @@ +/* + * "The way things are connected" and a few setup options + * + * Copyright (C) 2014 Alexandru Gagniuc + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef _MAINBOARD_LENOVO_G505S_MAINBOARD_H +#define _MAINBOARD_LENOVO_G505S_MAINBOARD_H + +/* What is connected to GEVENT pins */ +#define EC_SCI_GEVENT 3 +#define EC_LID_GEVENT 22 +#define EC_SMI_GEVENT 23 +#define PCIE_GEVENT 8 + +/* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but + * we make the distinction between GEVENT pin and SCI. + */ +#define EC_SCI_GPE EC_SCI_GEVENT +#define EC_LID_GPE EC_LID_GEVENT +#define PME_GPE 0x0b +#define PCIE_GPE 0x18 + +#endif /* _MAINBOARD_LENOVO_G505S_MAINBOARD_H */ -- cgit v1.2.3