diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-03-12 01:22:01 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-23 09:35:51 +0000 |
| commit | 6975e07997cedf8a78f0704a461765dfe2a09fe6 (patch) | |
| tree | 138b7bee3e2482d7a95ad4dfb9bf0d401f7b97f0 /src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | |
| parent | 79a219813b3e8186f5e89b2e0cd9f8a921fa088f (diff) | |
mb/tglrvp: Update Audio AIC settings for Tiger Lake
Update Audio AIC UPD settings and gpio pad configs for Tiger Lake.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 41a361c016..23737c3070 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -101,7 +101,9 @@ chip soc/intel/tigerlake register "PchHdaAudioLinkDmicEnable[0]" = "1" register "PchHdaAudioLinkDmicEnable[1]" = "1" register "PchHdaAudioLinkSspEnable[0]" = "1" - register "PchHdaAudioLinkSspEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "0" + register "PchHdaAudioLinkSspEnable[2]" = "1" + register "PchHdaAudioLinkSndwEnable[0]" = "1" # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T register "PchHdaIDispLinkTmode" = "2" # iDisp-Link Freq 4: 96MHz, 3: 48MHz. |