From 6975e07997cedf8a78f0704a461765dfe2a09fe6 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Thu, 12 Mar 2020 01:22:01 -0700 Subject: mb/tglrvp: Update Audio AIC settings for Tiger Lake Update Audio AIC UPD settings and gpio pad configs for Tiger Lake. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39466 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb') diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 41a361c016..23737c3070 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -101,7 +101,9 @@ chip soc/intel/tigerlake register "PchHdaAudioLinkDmicEnable[0]" = "1" register "PchHdaAudioLinkDmicEnable[1]" = "1" register "PchHdaAudioLinkSspEnable[0]" = "1" - register "PchHdaAudioLinkSspEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "0" + register "PchHdaAudioLinkSspEnable[2]" = "1" + register "PchHdaAudioLinkSndwEnable[0]" = "1" # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T register "PchHdaIDispLinkTmode" = "2" # iDisp-Link Freq 4: 96MHz, 3: 48MHz. -- cgit v1.2.3