diff options
| author | Felix Singer <felixsinger@posteo.net> | 2023-10-23 07:26:28 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-25 14:16:16 +0000 |
| commit | 21b5a9aff41136bacb3cce78ae027cd588c74295 (patch) | |
| tree | 57ff2a980d3a8704f16c9d7cd80341b107840e82 /src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb | |
| parent | a41abea65d673d7c006dbde2ca832abdedd0bb2b (diff) | |
devicetrees: Remove trailing backslash from multiline values
It's not needed to put a backslash at the end of a line for quoted
multiline values. Thus, remove it.
Change-Id: I1b83d53598ba2adeed853a96d6c2c1a21f01a9f7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78576
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb')
| -rw-r--r-- | src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 2c93a38921..27652d0fe5 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -24,16 +24,16 @@ chip soc/intel/skylake #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = VR_CFG_AMP(7), \ - .voltage_limit = 1520 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520 }" # Enable Root ports. @@ -96,18 +96,18 @@ chip soc/intel/skylake register "SsicPortEnable" = "1" # Enable SSIC for WWAN # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoPci, \ - [PchSerialIoIndexI2C3] = PchSerialIoPci, \ - [PchSerialIoIndexI2C4] = PchSerialIoPci, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" device domain 0 on |