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authorFelix Singer <felixsinger@posteo.net>2023-10-23 07:26:28 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-10-25 14:16:16 +0000
commit21b5a9aff41136bacb3cce78ae027cd588c74295 (patch)
tree57ff2a980d3a8704f16c9d7cd80341b107840e82 /src/mainboard/intel/kblrvp/variants
parenta41abea65d673d7c006dbde2ca832abdedd0bb2b (diff)
devicetrees: Remove trailing backslash from multiline values
It's not needed to put a backslash at the end of a line for quoted multiline values. Thus, remove it. Change-Id: I1b83d53598ba2adeed853a96d6c2c1a21f01a9f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78576 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants')
-rw-r--r--src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb80
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb42
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb44
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb104
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb122
5 files changed, 196 insertions, 196 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
index bf1b235914..b015fc641c 100644
--- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
@@ -55,55 +55,55 @@ chip soc/intel/skylake
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20), \
- .psi2threshold = VR_CFG_AMP(4), \
- .psi3threshold = VR_CFG_AMP(1), \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0, \
- .imon_offset = 0, \
- .icc_max = VR_CFG_AMP(7), \
- .voltage_limit = 1520 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0,
+ .imon_offset = 0,
+ .icc_max = VR_CFG_AMP(7),
+ .voltage_limit = 1520
}"
register "domain_vr_config[VR_IA_CORE]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20), \
- .psi2threshold = VR_CFG_AMP(5), \
- .psi3threshold = VR_CFG_AMP(1), \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0, \
- .imon_offset = 0, \
- .icc_max = VR_CFG_AMP(34), \
- .voltage_limit = 1520 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0,
+ .imon_offset = 0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20), \
- .psi2threshold = VR_CFG_AMP(5), \
- .psi3threshold = VR_CFG_AMP(1), \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0, \
- .imon_offset = 0, \
- .icc_max = VR_CFG_AMP(35),\
- .voltage_limit = 1520 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0,
+ .imon_offset = 0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20), \
- .psi2threshold = VR_CFG_AMP(5), \
- .psi3threshold = VR_CFG_AMP(1), \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0, \
- .imon_offset = 0, \
- .icc_max = VR_CFG_AMP(35), \
- .voltage_limit = 1520 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0,
+ .imon_offset = 0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520
}"
# Send an extra VR mailbox command for the PS4 exit issue
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index d512814023..f1ad6a2385 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -73,28 +73,28 @@ chip soc/intel/skylake
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
register "SataSalpSupport" = "1"
- register "SataPortsEnable" = "{ \
- [0] = 1, \
- [1] = 1, \
- [2] = 1, \
- [3] = 1, \
- [4] = 1, \
- [5] = 1, \
- [6] = 1, \
- [7] = 1, \
+ register "SataPortsEnable" = "{
+ [0] = 1,
+ [1] = 1,
+ [2] = 1,
+ [3] = 1,
+ [4] = 1,
+ [5] = 1,
+ [6] = 1,
+ [7] = 1,
}"
- register "SerialIoDevMode" = "{ \
- [PchSerialIoIndexI2C0] = PchSerialIoPci, \
- [PchSerialIoIndexI2C1] = PchSerialIoPci, \
- [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart0] = PchSerialIoPci, \
- [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart0] = PchSerialIoPci,
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
# PL2 override 60W
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index 2c93a38921..27652d0fe5 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -24,16 +24,16 @@ chip soc/intel/skylake
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20), \
- .psi2threshold = VR_CFG_AMP(5), \
- .psi3threshold = VR_CFG_AMP(1), \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0, \
- .imon_offset = 0, \
- .icc_max = VR_CFG_AMP(7), \
- .voltage_limit = 1520 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0,
+ .imon_offset = 0,
+ .icc_max = VR_CFG_AMP(7),
+ .voltage_limit = 1520
}"
# Enable Root ports.
@@ -96,18 +96,18 @@ chip soc/intel/skylake
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
# Must leave UART0 enabled or SD/eMMC will not work as PCI
- register "SerialIoDevMode" = "{ \
- [PchSerialIoIndexI2C0] = PchSerialIoPci, \
- [PchSerialIoIndexI2C1] = PchSerialIoPci, \
- [PchSerialIoIndexI2C2] = PchSerialIoPci, \
- [PchSerialIoIndexI2C3] = PchSerialIoPci, \
- [PchSerialIoIndexI2C4] = PchSerialIoPci, \
- [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart0] = PchSerialIoPci, \
- [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart0] = PchSerialIoPci,
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
device domain 0 on
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
index 23cbf96f40..3a75b486be 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
@@ -29,55 +29,55 @@ chip soc/intel/skylake
#* VrVoltageLimit command not sent.
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20), \
- .psi2threshold = VR_CFG_AMP(5), \
- .psi3threshold = VR_CFG_AMP(1), \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0, \
- .imon_offset = 0, \
- .icc_max = 0, \
- .voltage_limit = 0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0,
+ .imon_offset = 0,
+ .icc_max = 0,
+ .voltage_limit = 0
}"
register "domain_vr_config[VR_IA_CORE]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20), \
- .psi2threshold = VR_CFG_AMP(5), \
- .psi3threshold = VR_CFG_AMP(1), \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0, \
- .imon_offset = 0, \
- .icc_max = 0, \
- .voltage_limit = 0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0,
+ .imon_offset = 0,
+ .icc_max = 0,
+ .voltage_limit = 0
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20), \
- .psi2threshold = VR_CFG_AMP(5), \
- .psi3threshold = VR_CFG_AMP(1), \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0, \
- .imon_offset = 0, \
- .icc_max = 0 ,\
- .voltage_limit = 0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0,
+ .imon_offset = 0,
+ .icc_max = 0,
+ .voltage_limit = 0
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20), \
- .psi2threshold = VR_CFG_AMP(5), \
- .psi3threshold = VR_CFG_AMP(1), \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0, \
- .imon_offset = 0, \
- .icc_max = 0, \
- .voltage_limit = 0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0,
+ .imon_offset = 0,
+ .icc_max = 0,
+ .voltage_limit = 0
}"
# Enable Root ports.
@@ -133,18 +133,18 @@ chip soc/intel/skylake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
- register "SerialIoDevMode" = "{ \
- [PchSerialIoIndexI2C0] = PchSerialIoPci, \
- [PchSerialIoIndexI2C1] = PchSerialIoPci, \
- [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C4] = PchSerialIoPci, \
- [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart0] = PchSerialIoPci, \
- [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart0] = PchSerialIoPci,
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
# Use default SD card detect GPIO configuration
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 869539647a..6d51f440c0 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -26,55 +26,55 @@ chip soc/intel/skylake
#* VrVoltageLimit command not sent.
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20), \
- .psi2threshold = VR_CFG_AMP(4), \
- .psi3threshold = VR_CFG_AMP(1), \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0, \
- .imon_offset = 0, \
- .icc_max = 0, \
- .voltage_limit = 0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0,
+ .imon_offset = 0,
+ .icc_max = 0,
+ .voltage_limit = 0
}"
register "domain_vr_config[VR_IA_CORE]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20), \
- .psi2threshold = VR_CFG_AMP(5), \
- .psi3threshold = VR_CFG_AMP(1), \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0, \
- .imon_offset = 0, \
- .icc_max = 0, \
- .voltage_limit = 0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0,
+ .imon_offset = 0,
+ .icc_max = 0,
+ .voltage_limit = 0
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20), \
- .psi2threshold = VR_CFG_AMP(5), \
- .psi3threshold = VR_CFG_AMP(1), \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0, \
- .imon_offset = 0, \
- .icc_max = 0 ,\
- .voltage_limit = 0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0,
+ .imon_offset = 0,
+ .icc_max = 0,
+ .voltage_limit = 0
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20), \
- .psi2threshold = VR_CFG_AMP(5), \
- .psi3threshold = VR_CFG_AMP(1), \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0, \
- .imon_offset = 0, \
- .icc_max = 0, \
- .voltage_limit = 0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0,
+ .imon_offset = 0,
+ .icc_max = 0,
+ .voltage_limit = 0
}"
# Enable Root port.
@@ -124,30 +124,30 @@ chip soc/intel/skylake
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
register "SataSalpSupport" = "1"
- register "SataPortsEnable" = "{ \
- [0] = 1, \
- [1] = 1, \
- [2] = 1, \
- [3] = 1, \
- [4] = 1, \
- [5] = 1, \
- [6] = 1, \
- [7] = 1, \
+ register "SataPortsEnable" = "{
+ [0] = 1,
+ [1] = 1,
+ [2] = 1,
+ [3] = 1,
+ [4] = 1,
+ [5] = 1,
+ [6] = 1,
+ [7] = 1,
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
- register "SerialIoDevMode" = "{ \
- [PchSerialIoIndexI2C0] = PchSerialIoPci, \
- [PchSerialIoIndexI2C1] = PchSerialIoPci, \
- [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart0] = PchSerialIoPci, \
- [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart0] = PchSerialIoPci,
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
# PL2 override 25W
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 19:35:57 +0000