diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 21:39:55 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:44:19 +0000 |
| commit | 576f1cd44b89c0436332200ca35ccd9f9bb54815 (patch) | |
| tree | 4019fb124225349ff09b09fa94e60bbbf6cf5d3c /src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb | |
| parent | 4b7220398923af42fa39a7fcb532daf797510f77 (diff) | |
skl mainboards/dt: Move SsicPortEnable setting into XHCI device scope
Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83189
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb')
| -rw-r--r-- | src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 8a3161a41f..9d4c0d9286 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -41,10 +41,6 @@ chip soc/intel/skylake # RP17, uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7" - # USB related - register "SsicPortEnable" = "1" - - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -66,6 +62,8 @@ chip soc/intel/skylake device domain 0 on device ref south_xhci on + register "SsicPortEnable" = "1" + register "usb2_ports" = "{ [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ [1] = USB2_PORT_MID(OC3), /* Touch Pad */ |