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authorMartin Roth <gaumless@gmail.com>2023-10-23 09:59:09 -0600
committerFelix Held <felix-coreboot@felixheld.de>2023-10-25 14:06:37 +0000
commit58964ff02ce7a78bc698f424fd0834aad930e1af (patch)
tree248869b0b05c00a54d33a93500f4dceb4315453e /src/mainboard/intel/kblrvp/smihandler.c
parent7039edd2da302bb63dc8930a8492b5d6940d7e33 (diff)
include/device/dram: Add SPD lengths for DDR3 to DDR5
DDR2 already had a define to specify the SPD length, but other memory types did not. This led to the value being coded into other locations. Unify the definition for DDR2 to DDR5 and put the value at the top of the respective header file. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id13b9c5d311984d4a98b831a8746d1659724aa96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/mainboard/intel/kblrvp/smihandler.c')
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