summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/include/device/dram/ddr2.h6
-rw-r--r--src/include/device/dram/ddr3.h3
-rw-r--r--src/include/device/dram/ddr4.h3
-rw-r--r--src/include/device/dram/ddr5.h3
4 files changed, 12 insertions, 3 deletions
diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h
index 9277ffbc02..032d5ce4cc 100644
--- a/src/include/device/dram/ddr2.h
+++ b/src/include/device/dram/ddr2.h
@@ -18,6 +18,9 @@
#include <spd.h>
#include <device/dram/common.h>
+/** Maximum SPD size supported */
+#define SPD_SIZE_MAX_DDR2 128
+
/* Byte 20 [5:0]: DDR2 Module type information */
enum spd_dimm_type_ddr2 {
SPD_DDR2_DIMM_TYPE_UNDEFINED = 0x00,
@@ -151,9 +154,6 @@ struct dimm_attr_ddr2_st {
u32 serial;
};
-/** Maximum SPD size supported */
-#define SPD_SIZE_MAX_DDR2 128
-
int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type);
u8 spd_ddr2_calc_checksum(u8 *spd, int len);
u32 spd_decode_spd_size_ddr2(u8 byte0);
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index 8886e64ac8..6efe0494df 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -19,6 +19,9 @@
#include <device/dram/common.h>
#include <types.h>
+/** Maximum SPD size supported */
+#define SPD_SIZE_MAX_DDR3 256
+
/**
* Convenience definitions for SPD offsets
*
diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h
index 6b05288fd7..7210212520 100644
--- a/src/include/device/dram/ddr4.h
+++ b/src/include/device/dram/ddr4.h
@@ -18,6 +18,9 @@
#include <device/dram/common.h>
#include <types.h>
+/** Maximum SPD size supported */
+#define SPD_SIZE_MAX_DDR4 512
+
#define SPD_DDR4_PART_OFF 329
#define SPD_DDR4_PART_LEN 20
diff --git a/src/include/device/dram/ddr5.h b/src/include/device/dram/ddr5.h
index a509126371..ff1604a808 100644
--- a/src/include/device/dram/ddr5.h
+++ b/src/include/device/dram/ddr5.h
@@ -12,6 +12,9 @@
#include <device/dram/common.h>
#include <types.h>
+/** Maximum SPD size supported */
+#define SPD_SIZE_MAX_DDR5 1024
+
/**
* Converts DDR5 clock speed in MHz to the standard reported speed in MT/s
*/