diff options
| author | Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> | 2021-09-29 17:18:32 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-30 04:08:37 +0000 |
| commit | dab80422571e03919a7c70592e053a08f9e89df1 (patch) | |
| tree | bf0001325c1c434f663ded844975e85037f0c187 /src/mainboard/intel/adlrvp | |
| parent | e2816067202172e53dbbed9cc2bb52cc0f565216 (diff) | |
mb/google/brya/variants/gimble: Correct SSD power sequence
M.2 spec describes PERST# should be sequenced after power enable.
BUG=b:201512872
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie164ddb29f947e190fa87b31165e3c84b07926e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58034
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
0 files changed, 0 insertions, 0 deletions