diff options
| author | Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> | 2021-09-29 17:18:32 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-30 04:08:37 +0000 |
| commit | dab80422571e03919a7c70592e053a08f9e89df1 (patch) | |
| tree | bf0001325c1c434f663ded844975e85037f0c187 | |
| parent | e2816067202172e53dbbed9cc2bb52cc0f565216 (diff) | |
mb/google/brya/variants/gimble: Correct SSD power sequence
M.2 spec describes PERST# should be sequenced after power enable.
BUG=b:201512872
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie164ddb29f947e190fa87b31165e3c84b07926e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58034
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/gimble/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/gimble/gpio.c | 13 |
2 files changed, 14 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/gimble/Makefile.inc b/src/mainboard/google/brya/variants/gimble/Makefile.inc index acf9bada81..446d113a80 100644 --- a/src/mainboard/google/brya/variants/gimble/Makefile.inc +++ b/src/mainboard/google/brya/variants/gimble/Makefile.inc @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += gpio.c + ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/gimble/gpio.c b/src/mainboard/google/brya/variants/gimble/gpio.c index 8ce4f45453..b1c4ba058e 100644 --- a/src/mainboard/google/brya/variants/gimble/gpio.c +++ b/src/mainboard/google/brya/variants/gimble/gpio.c @@ -116,7 +116,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ @@ -151,6 +151,11 @@ static const struct pad_config early_gpio_table[] = { PAD_NC(GPP_H13, UP_20K), }; +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -162,3 +167,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} |