diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-10-28 13:25:06 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-29 10:49:03 +0000 |
| commit | b544fe48af76e5aae7537d95b62191e1fed2bc45 (patch) | |
| tree | 1a4ec089b065138d084dcedbf0d4f0f3e4eed752 /src/mainboard/intel/adlrvp/romstage_fsp_params.c | |
| parent | 68e597d81e41bb2d93558e4a4da26f0892f34d86 (diff) | |
mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'
List of changes:
1. Split mem_cfg for DDR4 and LPDDR4 as per board_id
2. Move dq_pins_interleaved into board-specific memory configuration
information
TEST=Able to build and boot DDR4 and LPDDR4 ADLRVP SKUs.
Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46873
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp/romstage_fsp_params.c')
| -rw-r--r-- | src/mainboard/intel/adlrvp/romstage_fsp_params.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 9d7cc9118f..209ee6a222 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -51,12 +51,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) switch (board_id) { case ADL_P_DDR4_1: case ADL_P_DDR4_2: - mupd->FspmConfig.DqPinsInterleaved = 1; memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated); break; case ADL_P_LP4_1: case ADL_P_LP4_2: - mupd->FspmConfig.DqPinsInterleaved = 0; memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated); break; default: |