From b544fe48af76e5aae7537d95b62191e1fed2bc45 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 28 Oct 2020 13:25:06 +0530 Subject: mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg' List of changes: 1. Split mem_cfg for DDR4 and LPDDR4 as per board_id 2. Move dq_pins_interleaved into board-specific memory configuration information TEST=Able to build and boot DDR4 and LPDDR4 ADLRVP SKUs. Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46873 Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/romstage_fsp_params.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mainboard/intel/adlrvp/romstage_fsp_params.c') diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 9d7cc9118f..209ee6a222 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -51,12 +51,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) switch (board_id) { case ADL_P_DDR4_1: case ADL_P_DDR4_2: - mupd->FspmConfig.DqPinsInterleaved = 1; memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated); break; case ADL_P_LP4_1: case ADL_P_LP4_2: - mupd->FspmConfig.DqPinsInterleaved = 0; memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated); break; default: -- cgit v1.2.3