| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-02-22 | mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17 | Subrata Banik |
| 2021-02-17 | mb/intel/adlrvp: Fix incorrect SPD address issue on DDR4/DDR5 | Subrata Banik |
| 2021-02-16 | mb/{intel,prodrive,protectli}: Remove unused <string.h> | Elyes HAOUAS |
| 2021-02-04 | src: Remove unused <cbfs.h> | Elyes HAOUAS |
| 2021-01-25 | soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver | Furquan Shaikh |
| 2020-12-01 | mb/intel/adlrvp: Add support for LPDDR5 | Sridhar Siricilla |
| 2020-11-05 | mb/intel/adlrvp: Add support for DDR5 memory | Subrata Banik |
| 2020-10-29 | mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg' | Subrata Banik |
| 2020-10-11 | mb/intel/adlrvp: Add ADL-P romstage mainboard code | Subrata Banik |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |