diff options
| author | Keith Hui <buurin@gmail.com> | 2023-07-22 12:49:05 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-13 20:31:23 +0000 |
| commit | 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da (patch) | |
| tree | 8b0fb3b07ecb3cfa84aa77b51c0e1053a1415c73 /src/mainboard/hp/compaq_elite_8300_usdt | |
| parent | 940fe080bf1ed2dac827b569c70fb0ea11496041 (diff) | |
mb/*: Update SPD mapping for sandybridge boards
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.
Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.
Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/mainboard/hp/compaq_elite_8300_usdt')
| -rw-r--r-- | src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/hp/compaq_elite_8300_usdt/early_init.c | 9 |
2 files changed, 2 insertions, 9 deletions
diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb index f7f321fc83..7a62df1001 100644 --- a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb +++ b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb @@ -1,6 +1,8 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" + # BTX mainboard: Reversed mapping + register "spd_addresses" = "{0, 0x52, 0, 0x50}" device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "0" diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c b/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c index 857c25dd19..ae75d7c32a 100644 --- a/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c +++ b/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c @@ -1,14 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include <bootblock_common.h> #include <superio/nuvoton/npcd378/npcd378.h> #include <superio/nuvoton/common/nuvoton.h> #include <device/pci_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, @@ -31,9 +28,3 @@ void bootblock_mainboard_early_init(void) pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1408); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[3], 0x50, id_only); - read_spd(&spd[1], 0x52, id_only); -} |