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authorKun Liu <liukun11@huaqin.corp-partner.google.com>2023-08-07 16:16:18 +0800
committerSubrata Banik <subratabanik@google.com>2023-08-08 10:14:20 +0000
commit961a88a115cfc5e59f3b487145654cdf7ba8653d (patch)
tree5ea4527654f5cb00ec1653d14ae20a08aa716449 /src/mainboard/google
parentfdb3d07502444752abfd1714d3dfe976cb17e30b (diff)
mb/google/rex/var/screebo: Change sdcard clk from 7 to 6
Update firmware to reflect schematics change for SD Card CLKSRC from 7 to 6 for EVT board revision BUG=b:291051683 TEST=emerge-rex coreboot Change-Id: I3347f739650458c833d5a825742cf1d663853cc5 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77023 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/rex/variants/screebo/overridetree.cb8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index 9320011a05..ee7469d602 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -245,17 +245,17 @@ chip soc/intel/meteorlake
end
end # PCIE4_P9 SSD card
device ref pcie_rp10 on
- # Enable SD Card PCIE4 rp10 using clk 7
+ # Enable SD Card PCIE4 rp10 using clk 6
register "pcie_rp[PCH_RP(10)]" = "{
- .clk_src = 7,
- .clk_req = 7,
+ .clk_src = 6,
+ .clk_req = 6,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L1,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)"
- register "srcclk_pin" = "7"
+ register "srcclk_pin" = "6"
device generic 0 on
probe DB_SD SD_GL9750
probe DB_SD SD_RTS5227S