From 961a88a115cfc5e59f3b487145654cdf7ba8653d Mon Sep 17 00:00:00 2001 From: Kun Liu Date: Mon, 7 Aug 2023 16:16:18 +0800 Subject: mb/google/rex/var/screebo: Change sdcard clk from 7 to 6 Update firmware to reflect schematics change for SD Card CLKSRC from 7 to 6 for EVT board revision BUG=b:291051683 TEST=emerge-rex coreboot Change-Id: I3347f739650458c833d5a825742cf1d663853cc5 Signed-off-by: Kun Liu Reviewed-on: https://review.coreboot.org/c/coreboot/+/77023 Reviewed-by: Subrata Banik Reviewed-by: Kapil Porwal Reviewed-by: Rui Zhou Tested-by: build bot (Jenkins) --- src/mainboard/google/rex/variants/screebo/overridetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 9320011a05..ee7469d602 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -245,17 +245,17 @@ chip soc/intel/meteorlake end end # PCIE4_P9 SSD card device ref pcie_rp10 on - # Enable SD Card PCIE4 rp10 using clk 7 + # Enable SD Card PCIE4 rp10 using clk 6 register "pcie_rp[PCH_RP(10)]" = "{ - .clk_src = 7, - .clk_req = 7, + .clk_src = 6, + .clk_req = 6, .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, .pcie_rp_aspm = ASPM_L1, }" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)" - register "srcclk_pin" = "7" + register "srcclk_pin" = "6" device generic 0 on probe DB_SD SD_GL9750 probe DB_SD SD_RTS5227S -- cgit v1.2.3