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authorFelix Singer <felixsinger@posteo.net>2024-06-27 22:58:52 +0200
committerFelix Singer <felixsinger@posteo.net>2024-06-29 20:03:50 +0000
commitbc8f5405b542eef35a71e5189d71654cbe134558 (patch)
tree289b1339565fb614281b31e07f09bb933c1465b8 /src/mainboard/google/volteer/variants/voema/overridetree.cb
parent0adf35537bd6093b79b1701becee823d3436d975 (diff)
tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/google/volteer/variants/voema/overridetree.cb')
-rw-r--r--src/mainboard/google/volteer/variants/voema/overridetree.cb8
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb
index 4c83c7e42d..97160ee269 100644
--- a/src/mainboard/google/volteer/variants/voema/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb
@@ -5,9 +5,6 @@ chip soc/intel/tigerlake
# and controller 1 channel 0 and 1.
register "CmdMirror" = "0x00000033"
- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Port 1
- register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Port 0
-
register "TcssAuxOri" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
@@ -159,6 +156,11 @@ chip soc/intel/tigerlake
end
end
device ref south_xhci on
+ register "usb2_ports" = "{
+ [2] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C Port 1
+ [4] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C Port 0
+ }"
+
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi