diff options
author | David Hendricks <dhendrix@chromium.org> | 2014-11-06 16:51:02 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-10 20:50:16 +0200 |
commit | 539e856643f9a7396638c05db5c4dbfb136e292b (patch) | |
tree | 5d07a3d65a633575a199063114d518ea3ed37cb1 /src/mainboard/google/veyron_jerry/boardid.c | |
parent | a0abd51e4edb6b00c82032234b8ae1868e6d965e (diff) |
veyron*: sdram_get_ram_code() -> ram_code()
This enables RAM_CODE_SUPPORT for veyron* platforms and uses the
generic gpio_get_binaries() function to read RAM_ID GPIOs.
BUG=chrome-os-partner:31728
BRANCH=none
TEST=built and booted on pinky
Change-Id: I7a03e42a270bec7036004375d36734bfdfe6e528
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a325b204ff88131dfb0bdd3dfedb3c007cd98010
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Ibc4c61687f1c59311cbf6b48371f9a9125dbe115
Original-Reviewed-on: https://chromium-review.googlesource.com/227249
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9549
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/veyron_jerry/boardid.c')
-rw-r--r-- | src/mainboard/google/veyron_jerry/boardid.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/veyron_jerry/boardid.c b/src/mainboard/google/veyron_jerry/boardid.c index 66de2768f2..513754f048 100644 --- a/src/mainboard/google/veyron_jerry/boardid.c +++ b/src/mainboard/google/veyron_jerry/boardid.c @@ -35,3 +35,15 @@ uint8_t board_id(void) return id; } + +uint32_t ram_code(void) +{ + uint32_t code; + static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), + [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ + + code = gpio_base2_value(pins, ARRAY_SIZE(pins)); + printk(BIOS_SPEW, "RAM Config: %u.\n", code); + + return code; +} |