From 539e856643f9a7396638c05db5c4dbfb136e292b Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Thu, 6 Nov 2014 16:51:02 -0800 Subject: veyron*: sdram_get_ram_code() -> ram_code() This enables RAM_CODE_SUPPORT for veyron* platforms and uses the generic gpio_get_binaries() function to read RAM_ID GPIOs. BUG=chrome-os-partner:31728 BRANCH=none TEST=built and booted on pinky Change-Id: I7a03e42a270bec7036004375d36734bfdfe6e528 Signed-off-by: Patrick Georgi Original-Commit-Id: a325b204ff88131dfb0bdd3dfedb3c007cd98010 Original-Signed-off-by: David Hendricks Original-Change-Id: Ibc4c61687f1c59311cbf6b48371f9a9125dbe115 Original-Reviewed-on: https://chromium-review.googlesource.com/227249 Original-Reviewed-by: Julius Werner Reviewed-on: http://review.coreboot.org/9549 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/veyron_jerry/boardid.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/mainboard/google/veyron_jerry/boardid.c') diff --git a/src/mainboard/google/veyron_jerry/boardid.c b/src/mainboard/google/veyron_jerry/boardid.c index 66de2768f2..513754f048 100644 --- a/src/mainboard/google/veyron_jerry/boardid.c +++ b/src/mainboard/google/veyron_jerry/boardid.c @@ -35,3 +35,15 @@ uint8_t board_id(void) return id; } + +uint32_t ram_code(void) +{ + uint32_t code; + static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), + [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ + + code = gpio_base2_value(pins, ARRAY_SIZE(pins)); + printk(BIOS_SPEW, "RAM Config: %u.\n", code); + + return code; +} -- cgit v1.2.3