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authorElyes Haouas <ehaouas@noos.fr>2024-08-31 10:57:18 +0200
committerElyes Haouas <ehaouas@noos.fr>2024-09-01 04:58:51 +0000
commitb1ae6ca7ef8b848e53577cb9da46c19d2d5886a8 (patch)
tree8900b50b15d8934d7a1d8efc711ca8e7498ffe0d /src/mainboard/google/sarien
parentf3d54feef4c700991dd11b012f810162c5b6b06a (diff)
tree: Use boolean for s0ix_enable
Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/sarien')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb2
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index fcaa730240..7eec7a8724 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -27,7 +27,7 @@ chip soc/intel/cannonlake
# USB2 PHY Power gating
register "PchUsb2PhySusPgDisable" = "1"
- register "s0ix_enable" = "1"
+ register "s0ix_enable" = "true"
register "dptf_enable" = "1"
register "satapwroptimize" = "1"
register "power_limits_config" = "{
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 589ea1c3aa..d10fd1f2e6 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -30,7 +30,7 @@ chip soc/intel/cannonlake
# USB2 PHY Power gating
register "PchUsb2PhySusPgDisable" = "1"
- register "s0ix_enable" = "1"
+ register "s0ix_enable" = "true"
register "dptf_enable" = "1"
register "satapwroptimize" = "1"
register "AcousticNoiseMitigation" = "1"