diff options
| author | Furquan Shaikh <furquan@google.com> | 2018-03-14 19:57:16 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-03-16 04:43:01 +0000 |
| commit | 6d5e10c05d99c475e63bbe95012066f9c585cfb3 (patch) | |
| tree | 8cecb6956bed707c4a8900ab79c491ad87982698 /src/mainboard/google/reef/variants/sand | |
| parent | 211bb97c67ce704fb40abb6dd9971790652237e3 (diff) | |
soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ#
from mainboards instead of defining a separate property for each root
port. This allows us to use memcpy to copy the entire array into FSP
params as well as new properties for PCIe root ports can be added as
arrays in future CLs.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/reef/variants/sand')
| -rw-r--r-- | src/mainboard/google/reef/variants/sand/devicetree.cb | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index a6692e6bf7..e53af885e0 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -4,13 +4,13 @@ chip soc/intel/apollolake device lapic 0 on end end - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" # GPIO for PERST_0 # If the Board has PERST_0 signal, assign the GPIO |