diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2022-02-13 13:20:17 -0600 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-05-03 16:05:46 +0000 |
| commit | 5f662e9f752314248e9b0d4e6cc0067b65730768 (patch) | |
| tree | 97369c01ef22763eaa128ed810c24d608c9087e7 /src/mainboard/google/reef/variants/coral | |
| parent | d095fd8cf1042942f8ec3843d4e9846ef9940038 (diff) | |
mb/google/reef: Disable unused devices in devicetrees
The image processing unit (Iunit) and SoC UARTS are not used on any
reef boards.
Change-Id: Iacdf93b4952cbc63fc465f07d440463106527b8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/reef/variants/coral')
| -rw-r--r-- | src/mainboard/google/reef/variants/coral/devicetree.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index f1d6030854..9e44d86591 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -124,7 +124,7 @@ chip soc/intel/apollolake device pci 02.0 on # - Gen register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 03.0 on end # - Iunit + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI @@ -238,8 +238,8 @@ chip soc/intel/apollolake device pci 17.2 off end # - I2C 6 device pci 17.3 off end # - I2C 7 device pci 18.0 on end # - UART 0 - device pci 18.1 on end # - UART 1 - device pci 18.2 on end # - UART 2 + device pci 18.1 off end # - UART 1 + device pci 18.2 off end # - UART 2 device pci 18.3 off end # - UART 3 device pci 19.0 on end # - SPI 0 device pci 19.1 off end # - SPI 1 |