diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-07-08 04:29:39 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-07-12 20:08:01 +0000 |
| commit | 88bc0f1604494de0f87c6954c050e7ef4d1c4457 (patch) | |
| tree | 9492b3a04b2bf7c66ac8202d97b3441d9ccf9306 /src/mainboard/google/poppy/variants/nautilus | |
| parent | 702902d71fae63fd35362c82f2a369b42af1a77f (diff) | |
skl/kbl mainboards: Move PCIe related settings into their device scope
Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/google/poppy/variants/nautilus')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 5d312084dd..92d72f8ac2 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -129,19 +129,6 @@ chip soc/intel/skylake .dc_loadline = 420, }" - # Enable Root port 1. - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" - # RP 1 uses CLK SRC 1 - register "PcieRpClkSrcNumber[0]" = "1" - # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" - # RP 1, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[0]" = "1" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -380,6 +367,12 @@ chip soc/intel/skylake end end device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" device pci 00.0 on end |