skl/kbl mainboards: Move PCIe related settings into their device scope

Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>

7 files changed, 71 insertions, 127 deletions

diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 85a1e23a70..48b9a9206b 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -126,14 +126,6 @@ chip soc/intel/skylake
 		.dc_loadline = 425,
 	}"
 
-	# PCIe Root port 1 with SRCCLKREQ1# (WLAN)
-	register "PcieRpEnable[0]" = "1"
-	register "PcieRpClkReqSupport[0]" = "1"
-	register "PcieRpClkReqNumber[0]" = "1"
-	register "PcieRpClkSrcNumber[0]" = "1"
-	register "PcieRpAdvancedErrorReporting[0]" = "1"
-	register "PcieRpLtrEnable[0]" = "1"
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -326,6 +318,13 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp1		on
+			# WLAN
+			register "PcieRpEnable[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqNumber[0]" = "1"
+			register "PcieRpClkSrcNumber[0]" = "1"
+			register "PcieRpAdvancedErrorReporting[0]" = "1"
+			register "PcieRpLtrEnable[0]" = "1"
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW1_07" # GPP_B7
 				device pci 00.0 on end
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index c44b380d9f..17eee3010a 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -111,19 +111,6 @@ chip soc/intel/skylake
 		.dc_loadline = 420,
 	}"
 
-	# Enable Root port 1.
-	register "PcieRpEnable[0]" = "1"
-	# Enable CLKREQ#
-	register "PcieRpClkReqSupport[0]" = "1"
-	# RP 1 uses SRCCLKREQ1#
-	register "PcieRpClkReqNumber[0]" = "1"
-	# RP 1, Enable Advanced Error Reporting
-	register "PcieRpAdvancedErrorReporting[0]" = "1"
-	# RP 1, Enable Latency Tolerance Reporting Mechanism
-	register "PcieRpLtrEnable[0]" = "1"
-	# RP 1 uses CLK SRC 1
-	register "PcieRpClkSrcNumber[0]" = "1"
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -342,6 +329,12 @@ chip soc/intel/skylake
 		end
 		device ref i2c4			on end
 		device ref pcie_rp1		on
+			register "PcieRpEnable[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqNumber[0]" = "1"
+			register "PcieRpAdvancedErrorReporting[0]" = "1"
+			register "PcieRpLtrEnable[0]" = "1"
+			register "PcieRpClkSrcNumber[0]" = "1"
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW0_00"
 				device pci 00.0 on end
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 43c1b4b162..b97007710f 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -119,48 +119,6 @@ chip soc/intel/skylake
 		.dc_loadline = 310,
 	}"
 
-	# Root port 4 (x1)
-	#  PcieRpEnable:                 Enable root port
-	#  PcieRpClkReqSupport:          Enable CLKREQ#
-	#  PcieRpClkReqNumber:           Uses SRCCLKREQ1#
-	#  PcieRpClkSrcNumber:           Uses 1
-	#  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
-	#  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism
-	register "PcieRpEnable[3]" = "1"
-	register "PcieRpClkReqSupport[3]" = "1"
-	register "PcieRpClkReqNumber[3]" = "1"
-	register "PcieRpClkSrcNumber[3]" = "1"
-	register "PcieRpAdvancedErrorReporting[3]" = "1"
-	register "PcieRpLtrEnable[3]" = "1"
-
-	# Root port 5 (x4)
-	#  PcieRpEnable:                 Enable root port
-	#  PcieRpClkReqSupport:          Enable CLKREQ#
-	#  PcieRpClkReqNumber:           Uses SRCCLKREQ3#
-	#  PcieRpClkSrcNumber:           Uses 3
-	#  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
-	#  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism
-	register "PcieRpEnable[4]" = "1"
-	register "PcieRpClkReqSupport[4]" = "1"
-	register "PcieRpClkReqNumber[4]" = "3"
-	register "PcieRpClkSrcNumber[4]" = "3"
-	register "PcieRpAdvancedErrorReporting[4]" = "1"
-	register "PcieRpLtrEnable[4]" = "1"
-
-	# Root port 9 (x2)
-	#  PcieRpEnable:                 Enable root port
-	#  PcieRpClkReqSupport:          Enable CLKREQ#
-	#  PcieRpClkReqNumber:           Uses SRCCLKREQ2#
-	#  PcieRpClkSrcNumber:           Uses 2
-	#  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
-	#  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism
-	register "PcieRpEnable[8]" = "1"
-	register "PcieRpClkReqSupport[8]" = "1"
-	register "PcieRpClkReqNumber[8]" = "2"
-	register "PcieRpClkSrcNumber[8]" = "2"
-	register "PcieRpAdvancedErrorReporting[8]" = "1"
-	register "PcieRpLtrEnable[8]" = "1"
-
 	# Touchscreen
 	register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
 
@@ -419,16 +377,39 @@ chip soc/intel/skylake
 		device ref pcie_rp2		off end
 		device ref pcie_rp3		off end
 		device ref pcie_rp4		on
+			# x1
+			register "PcieRpEnable[3]" = "1"
+			register "PcieRpClkReqSupport[3]" = "1"
+			register "PcieRpClkReqNumber[3]" = "1"
+			register "PcieRpClkSrcNumber[3]" = "1"
+			register "PcieRpAdvancedErrorReporting[3]" = "1"
+			register "PcieRpLtrEnable[3]" = "1"
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22
 				device pci 00.0 on end
 			end
 		end
-		device ref pcie_rp5		on  end
+		device ref pcie_rp5		on
+			# x4
+			register "PcieRpEnable[4]" = "1"
+			register "PcieRpClkReqSupport[4]" = "1"
+			register "PcieRpClkReqNumber[4]" = "3"
+			register "PcieRpClkSrcNumber[4]" = "3"
+			register "PcieRpAdvancedErrorReporting[4]" = "1"
+			register "PcieRpLtrEnable[4]" = "1"
+		end
 		device ref pcie_rp6		off end
 		device ref pcie_rp7		off end
 		device ref pcie_rp8		off end
-		device ref pcie_rp9		on  end
+		device ref pcie_rp9		on
+			# x2
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqNumber[8]" = "2"
+			register "PcieRpClkSrcNumber[8]" = "2"
+			register "PcieRpAdvancedErrorReporting[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+		end
 		device ref pcie_rp10		off end
 		device ref pcie_rp11		off end
 		device ref pcie_rp12		off end
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 5d312084dd..92d72f8ac2 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -129,19 +129,6 @@ chip soc/intel/skylake
 		.dc_loadline = 420,
 	}"
 
-	# Enable Root port 1.
-	register "PcieRpEnable[0]" = "1"
-	# Enable CLKREQ#
-	register "PcieRpClkReqSupport[0]" = "1"
-	# RP 1 uses SRCCLKREQ1#
-	register "PcieRpClkReqNumber[0]" = "1"
-	# RP 1 uses CLK SRC 1
-	register "PcieRpClkSrcNumber[0]" = "1"
-	# RP 1, Enable Advanced Error Reporting
-	register "PcieRpAdvancedErrorReporting[0]" = "1"
-	# RP 1, Enable Latency Tolerance Reporting Mechanism
-	register "PcieRpLtrEnable[0]" = "1"
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -380,6 +367,12 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp1		on
+			register "PcieRpEnable[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqNumber[0]" = "1"
+			register "PcieRpClkSrcNumber[0]" = "1"
+			register "PcieRpAdvancedErrorReporting[0]" = "1"
+			register "PcieRpLtrEnable[0]" = "1"
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW0_00"
 				device pci 00.0 on end
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 9853f49f43..27b2f0bc0d 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -119,28 +119,6 @@ chip soc/intel/skylake
 		.dc_loadline = 430,
 	}"
 
-	# PCIe Root port 1 with SRCCLKREQ1#
-	register "PcieRpEnable[0]" = "1"
-	register "PcieRpClkReqSupport[0]" = "1"
-	register "PcieRpClkReqNumber[0]" = "1"
-	register "PcieRpClkSrcNumber[0]" = "1"
-	register "PcieRpAdvancedErrorReporting[0]" = "1"
-	register "PcieRpLtrEnable[0]" = "1"
-
-	# Root port 9 (x2)
-	#  PcieRpEnable:                 Enable root port
-	#  PcieRpClkReqSupport:          Enable CLKREQ#
-	#  PcieRpClkReqNumber:           Uses SRCCLKREQ2#
-	#  PcieRpClkSrcNumber:           Uses 3
-	#  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
-	#  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism
-	register "PcieRpEnable[8]" = "1"
-	register "PcieRpClkReqSupport[8]" = "1"
-	register "PcieRpClkReqNumber[8]" = "2"
-	register "PcieRpClkSrcNumber[8]" = "3"
-	register "PcieRpAdvancedErrorReporting[8]" = "1"
-	register "PcieRpLtrEnable[8]" = "1"
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -354,6 +332,12 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp1		on
+			register "PcieRpEnable[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqNumber[0]" = "1"
+			register "PcieRpClkSrcNumber[0]" = "1"
+			register "PcieRpAdvancedErrorReporting[0]" = "1"
+			register "PcieRpLtrEnable[0]" = "1"
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_01"
 				device pci 00.0 on end
@@ -366,7 +350,15 @@ chip soc/intel/skylake
 		device ref pcie_rp6		off end
 		device ref pcie_rp7		off end
 		device ref pcie_rp8		off end
-		device ref pcie_rp9		on  end
+		device ref pcie_rp9		on
+			# x2
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqNumber[8]" = "2"
+			register "PcieRpClkSrcNumber[8]" = "3"
+			register "PcieRpAdvancedErrorReporting[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+		end
 		device ref pcie_rp10		off end
 		device ref pcie_rp11		off end
 		device ref pcie_rp12		off end
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index fa5753773b..8c8eb7f046 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -118,19 +118,6 @@ chip soc/intel/skylake
 		.dc_loadline = 430,
 	}"
 
-	# Enable Root port 1.
-	register "PcieRpEnable[0]" = "1"
-	# Enable CLKREQ#
-	register "PcieRpClkReqSupport[0]" = "1"
-	# RP 1 uses SRCCLKREQ1#
-	register "PcieRpClkReqNumber[0]" = "1"
-	# RP 1 uses CLK SRC 1
-	register "PcieRpClkSrcNumber[0]" = "1"
-	# RP 1, Enable Advanced Error Reporting
-	register "PcieRpAdvancedErrorReporting[0]" = "1"
-	# RP 1, Enable Latency Tolerance Reporting Mechanism
-	register "PcieRpLtrEnable[0]" = "1"
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -339,6 +326,12 @@ chip soc/intel/skylake
 		end
 		device ref i2c4			off end
 		device ref pcie_rp1		on
+			register "PcieRpEnable[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqNumber[0]" = "1"
+			register "PcieRpClkSrcNumber[0]" = "1"
+			register "PcieRpAdvancedErrorReporting[0]" = "1"
+			register "PcieRpLtrEnable[0]" = "1"
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW0_00" # GPP_B0
 				device pci 00.0 on end
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index d7dea1536e..5cb0f7da13 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -120,19 +120,6 @@ chip soc/intel/skylake
 		.dc_loadline = 420,
 	}"
 
-	# Enable Root port 1.
-	register "PcieRpEnable[0]" = "1"
-	# Enable CLKREQ#
-	register "PcieRpClkReqSupport[0]" = "1"
-	# RP 1 uses SRCCLKREQ1#
-	register "PcieRpClkReqNumber[0]" = "1"
-	# RP 1, Enable Advanced Error Reporting
-	register "PcieRpAdvancedErrorReporting[0]" = "1"
-	# RP 1, Enable Latency Tolerance Reporting Mechanism
-	register "PcieRpLtrEnable[0]" = "1"
-	# RP 1 uses CLK SRC 1
-	register "PcieRpClkSrcNumber[0]" = "1"
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -325,6 +312,12 @@ chip soc/intel/skylake
 		end
 		device ref i2c4			on  end
 		device ref pcie_rp1		on
+			register "PcieRpEnable[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqNumber[0]" = "1"
+			register "PcieRpAdvancedErrorReporting[0]" = "1"
+			register "PcieRpLtrEnable[0]" = "1"
+			register "PcieRpClkSrcNumber[0]" = "1"
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PCI_EXP"
 				device pci 00.0 on end