diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-12-16 13:10:58 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-12-23 05:12:14 +0000 |
| commit | 4b85d46170ef44ab88b9cf844e3d3feaf9e7e89e (patch) | |
| tree | 23405bc1cbb8224ed4043e5a90a837b4966ea633 /src/mainboard/google/hatch/romstage.c | |
| parent | 09e7b998379225fb0b79e5fd2fb5ba9b95bd6961 (diff) | |
mb/google/hatch: Add memory init setup for hatch
This implementation adds below support:
1. Add support to read memory strap.
2. Add support to configure below memory parameters
-> rcomp resistor configuration
-> dqs mapping
-> ect and ca vref config
3. Include SPD configuration
BUG=b:120914069
BRANCH=None
TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot
Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30248
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/romstage.c')
| -rw-r--r-- | src/mainboard/google/hatch/romstage.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index b79feb8e1a..401f41f22b 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -13,8 +13,17 @@ * GNU General Public License for more details. */ +#include <baseboard/variants.h> +#include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct spd_info spd = { + .spd_by_index = true, + .spd_spec.spd_index = variant_memory_sku(), + }; + + cannonlake_memcfg_init(&memupd->FspmConfig, + variant_memory_params(), &spd); } |