From 4b85d46170ef44ab88b9cf844e3d3feaf9e7e89e Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Sun, 16 Dec 2018 13:10:58 +0530 Subject: mb/google/hatch: Add memory init setup for hatch This implementation adds below support: 1. Add support to read memory strap. 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include SPD configuration BUG=b:120914069 BRANCH=None TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/30248 Reviewed-by: Subrata Banik Reviewed-by: Shelley Chen Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/romstage.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/mainboard/google/hatch/romstage.c') diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index b79feb8e1a..401f41f22b 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -13,8 +13,17 @@ * GNU General Public License for more details. */ +#include +#include #include void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct spd_info spd = { + .spd_by_index = true, + .spd_spec.spd_index = variant_memory_sku(), + }; + + cannonlake_memcfg_init(&memupd->FspmConfig, + variant_memory_params(), &spd); } -- cgit v1.2.3