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authorKenneth Chan <kenneth.chan@quanta.corp-partner.google.com>2022-01-06 10:22:34 +0800
committerRaul Rangel <rrangel@chromium.org>2022-01-06 18:14:13 +0000
commitfc7a40fad988102711f914b45843f80ca9b090a5 (patch)
tree2ff5dcbffdd9000a56fc2588239186c322900471 /src/mainboard/google/guybrush
parente3411cda2e746613e31af95b45b7bbce803a0517 (diff)
mb/google/guybrush/var/dewatt: update USB3 settings for passing SI
Update tx/rx term control to 3 for passing USB3 port 0/1 SI. b:199468920 TEST= emerge-guybrush coreboot; build and pass USB3 SI. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I637207d7c657f6dd71d70694f9a5fb35f8294b64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
Diffstat (limited to 'src/mainboard/google/guybrush')
-rw-r--r--src/mainboard/google/guybrush/variants/dewatt/overridetree.cb16
1 files changed, 15 insertions, 1 deletions
diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
index 9a9e760de6..e14ae4a575 100644
--- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
@@ -18,7 +18,7 @@ chip soc/amd/cezanne
register "telemetry_vddcrsocfull_scale_current_mA" = "31481" #mA
register "telemetry_vddcrsocoffset" = "193"
- #USB 2.0 phy config
+ #USB 2/3 phy config
register "usb_phy" = "{
/* Left USB C0 Port */
.Usb2PhyPort[0] = {
@@ -56,6 +56,20 @@ chip soc/amd/cezanne
.txhsxvtune = 3,
.txrestune = 1,
},
+ /* Left USB C0 Port */
+ .Usb3PhyPort[0] = {
+ .tx_term_ctrl=3,
+ .rx_term_ctrl=3,
+ .tx_vboost_lvl_en=1,
+ .tx_vboost_lvl=5,
+ },
+ /* Left USB A0 Port */
+ .Usb3PhyPort[1] = {
+ .tx_term_ctrl=3,
+ .rx_term_ctrl=3,
+ .tx_vboost_lvl_en=1,
+ .tx_vboost_lvl=5,
+ },
}"
# general purpose PCIe clock output configuration