diff options
| author | Martin Roth <martinroth@chromium.org> | 2021-05-20 20:41:18 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-06-29 18:06:13 +0000 |
| commit | 33608626872c5acca9a353d4b12b8fe8c8d2e8c7 (patch) | |
| tree | 4ca06c61fb24f222ca9f7850471d14a04c265a92 /src/mainboard/google/guybrush/Makefile.inc | |
| parent | 324cea9d1b3aa38d115522c67630cad510f6018e (diff) | |
mb/google/guybrush: Update romstage power-on timings for PCIe
This configures the romstage portion of the PCIe GPIOs in the correct
sequence to meet the power-on timings.
The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe
devices out of reset, both need to be brought hign.
BUG=b:184796302, b:184598323
TEST=Verify timings between GPIO init sections. All available modules
are present after training.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/guybrush/Makefile.inc')
| -rw-r--r-- | src/mainboard/google/guybrush/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index d4eeaf5e56..ecd031a85f 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -11,6 +11,7 @@ $(info APCB sources not found. Skipping APCB.) endif romstage-y += port_descriptors.c +romstage-y += romstage.c ramstage-y += mainboard.c ramstage-y += ec.c |