From 33608626872c5acca9a353d4b12b8fe8c8d2e8c7 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 20 May 2021 20:41:18 -0600 Subject: mb/google/guybrush: Update romstage power-on timings for PCIe This configures the romstage portion of the PCIe GPIOs in the correct sequence to meet the power-on timings. The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe devices out of reset, both need to be brought hign. BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training. Signed-off-by: Martin Roth Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/mainboard/google/guybrush/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/guybrush/Makefile.inc') diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index d4eeaf5e56..ecd031a85f 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -11,6 +11,7 @@ $(info APCB sources not found. Skipping APCB.) endif romstage-y += port_descriptors.c +romstage-y += romstage.c ramstage-y += mainboard.c ramstage-y += ec.c -- cgit v1.2.3