diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 00:25:18 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:43:56 +0000 |
| commit | 6c83a71b0a803c922b02b613e927d4c49b944c32 (patch) | |
| tree | 176f163e7fdeaaf1032c853e87ce5571bd921be7 /src/mainboard/google/glados/variants/chell/overridetree.cb | |
| parent | c7c8cf2edd713fd578423bc043403ae4f91e2e29 (diff) | |
skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/google/glados/variants/chell/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/glados/variants/chell/overridetree.cb | 29 |
1 files changed, 17 insertions, 12 deletions
diff --git a/src/mainboard/google/glados/variants/chell/overridetree.cb b/src/mainboard/google/glados/variants/chell/overridetree.cb index 9e4b7f0fc7..8ab7c35960 100644 --- a/src/mainboard/google/glados/variants/chell/overridetree.cb +++ b/src/mainboard/google/glados/variants/chell/overridetree.cb @@ -3,18 +3,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms - register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-C Port 2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # SD - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD - # PL2 override 15W register "power_limits_config" = "{ .tdp_pl2_override = 15, @@ -27,6 +15,23 @@ chip soc/intel/skylake register "tcc_offset" = "10" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC2), // Type-C Port 1 + [1] = USB2_PORT_LONG(OC3), // Type-C Port 2 + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [4] = USB2_PORT_MID(OC0), // Type-A Port + [6] = USB2_PORT_FLEX(OC_SKIP), // Camera + [8] = USB2_PORT_MID(OC_SKIP), // SD + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC2), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC3), // Type-C Port 2 + [2] = USB3_PORT_DEFAULT(OC0), // Type-A Port + [3] = USB3_PORT_DEFAULT(OC_SKIP), // SD + }" + end device ref i2c1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" |