skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope

Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>

18 files changed, 285 insertions, 214 deletions

diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index a2b4311d1e..e6a4178a3a 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -141,15 +141,6 @@ chip soc/intel/skylake
 	#RP 5 uses CLK SRC 4
 	register "PcieRpClkSrcNumber[4]" = "4"
 
-	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 2
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# H1
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -229,6 +220,18 @@ chip soc/intel/skylake
 		device ref igpu		on  end
 		device ref sa_thermal	on  end
 		device ref south_xhci	on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_LONG(OC0),	// Type-C Port 1
+				[1] = USB2_PORT_FLEX(OC_SKIP),	// Camera
+				[2] = USB2_PORT_MID(OC_SKIP),	// Bluetooth
+				[4] = USB2_PORT_LONG(OC1),	// Type-C Port 2
+				[6] = USB2_PORT_MID(OC_SKIP),	// H1
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	// Type-C Port 1
+				[1] = USB3_PORT_DEFAULT(OC1),	// Type-C Port 2
+			}"
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index d64a9f9102..a6ec6b62f8 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -233,22 +233,6 @@ chip soc/intel/skylake
 	# RP 12 uses CLK SRC 2
 	register "PcieRpClkSrcNumber[11]" = "2"
 
-	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"		# Type-A Rear
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC2)"		# Type-A Front
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC2)"		# Type-A Front
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC1)"		# Type-A Rear
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC1)"		# Type-A Rear
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"     # Type-A 2.0 / Debug
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Rear
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Front
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Front
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"	# Type-A Rear
-	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"	# Type-A Rear
-
 	register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"		# HDMI CEC
 	register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"		# TPM
 	register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3"		# Debug
@@ -306,6 +290,25 @@ chip soc/intel/skylake
 		device ref igpu		on  end
 		device ref sa_thermal	on  end
 		device ref south_xhci		on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_LONG(OC0),	// Type-C
+				[1] = USB2_PORT_MID(OC3),	// Type-A Rear
+				[2] = USB2_PORT_MID(OC2),	// Type-A Front
+				[3] = USB2_PORT_MID(OC2),	// Type-A Front
+				[4] = USB2_PORT_MID(OC1),	// Type-A Rear
+				[5] = USB2_PORT_MID(OC1),	// Type-A Rear
+				[6] = USB2_PORT_MID(OC_SKIP),	// Bluetooth
+				[7] = USB2_PORT_MID(OC_SKIP),	// Type-A 2.0 / Debug
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	// Type-C
+				[1] = USB3_PORT_DEFAULT(OC3),	// Type-A Rear
+				[2] = USB3_PORT_DEFAULT(OC2),	// Type-A Front
+				[3] = USB3_PORT_DEFAULT(OC2),	// Type-A Front
+				[4] = USB3_PORT_DEFAULT(OC1),	// Type-A Rear
+				[5] = USB3_PORT_DEFAULT(OC1),	// Type-A Rear
+			}"
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
index 989b2406fb..3da4f0e4f6 100644
--- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
+++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
@@ -42,20 +42,6 @@ chip soc/intel/skylake
 	register "PcieRpEnable[10]" = "0"
 	register "PcieRpEnable[11]" = "0"
 
-	register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)"	# Type-C
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# HDMI
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC2)"		# Type-A Rear
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC2)"		# Type-A Rear
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"		# Type-A Rear
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# HDMI Audio
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# HDMI
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Rear
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Rear
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Rear
-
 	register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"		# TPU
 	register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"		# TPM
 	register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"		# None
@@ -78,6 +64,23 @@ chip soc/intel/skylake
 
 	device domain 0 on
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_LONG(OC_SKIP),	// Type-C
+				[1] = USB2_PORT_MID(OC_SKIP),	// HDMI
+				[2] = USB2_PORT_MID(OC2),	// Type-A Rear
+				[3] = USB2_PORT_MID(OC2),	// Type-A Rear
+				[4] = USB2_PORT_MID(OC3),	// Type-A Rear
+				[5] = USB2_PORT_MID(OC_SKIP),	// HDMI Audio
+				[6] = USB2_PORT_MID(OC_SKIP),	// Bluetooth
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC_SKIP),	// Type-C
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	// HDMI
+				[2] = USB3_PORT_DEFAULT(OC2),		// Type-A Rear
+				[3] = USB3_PORT_DEFAULT(OC2),		// Type-A Rear
+				[4] = USB3_PORT_DEFAULT(OC3),		// Type-A Rear
+			}"
 			chip drivers/usb/acpi
 				device usb 0.0 on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb
index d1dc46f45a..25b39f4fbe 100644
--- a/src/mainboard/google/fizz/variants/karma/overridetree.cb
+++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb
@@ -1,28 +1,32 @@
 chip soc/intel/skylake
 
-	# Mapping of USB port # to device
-	#+----------------+-------+-----------------------------------+
-	#| Device         | Port# | Rev                               |
-	#+----------------+-------+-----------------------------------+
-	#| USB A Side     |   3   | 2/3                               |
-	#| SD Card        |   4   |                                   |
-	#| Camera         |   8   |                                   |
-	#| Touchsreen     |   10  |                                   |
-	#+----------------+-------+-----------------------------------+
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC2)"		# Type-A Side
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Card reader
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"     # Camera
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Touchscreen
-
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Side
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Card reader
-
 	register "power_limits_config" = "{
 		.psys_pmax = 151,
 	}"
 
 	device domain 0 on
 		device ref south_xhci on
+			# Mapping of USB port # to device
+			#+----------------+-------+-----------------------------------+
+			#| Device         | Port# | Rev                               |
+			#+----------------+-------+-----------------------------------+
+			#| USB A Side     |   3   | 2/3                               |
+			#| SD Card        |   4   |                                   |
+			#| Camera         |   8   |                                   |
+			#| Touchsreen     |   10  |                                   |
+			#+----------------+-------+-----------------------------------+
+			register "usb2_ports" = "{
+				[2] = USB2_PORT_MID(OC2),	// Type-A Side
+				[3] = USB2_PORT_MID(OC_SKIP),	// Card reader
+				[7] = USB2_PORT_MID(OC_SKIP),	// Camera
+				[9] = USB2_PORT_MID(OC_SKIP),	// Touchscreen
+			}"
+
+			register "usb3_ports" = "{
+				[2] = USB3_PORT_DEFAULT(OC2),		// Type-A Side
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// Card reader
+			}"
+
 			chip drivers/usb/acpi
 				device usb 0.0 on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/glados/variants/asuka/overridetree.cb b/src/mainboard/google/glados/variants/asuka/overridetree.cb
index 61220eee90..85b01554ac 100644
--- a/src/mainboard/google/glados/variants/asuka/overridetree.cb
+++ b/src/mainboard/google/glados/variants/asuka/overridetree.cb
@@ -1,19 +1,24 @@
 chip soc/intel/skylake
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC2)"		# Card Reader
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"		# Type-A Port (board)
-	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# PIC MCU
-	register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)"	# Type-A Port (board)
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Card Reader
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Port (board)
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Port (board)
-
 	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_TYPE_C(OC0),	// Type-C Port 1
+				[1] = USB2_PORT_MID(OC2),	// Card Reader
+				[2] = USB2_PORT_MID(OC_SKIP),	// Bluetooth
+				[4] = USB2_PORT_MID(OC2),	// Type-A Port (board)
+				[6] = USB2_PORT_FLEX(OC_SKIP),	// Camera
+				[7] = USB2_PORT_MID(OC_SKIP),	// PIC MCU
+				[8] = USB2_PORT_LONG(OC3),	// Type-A Port (board)
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),		// Type-C Port 1
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	// Card Reader
+				[2] = USB3_PORT_DEFAULT(OC2),		// Type-A Port (board)
+				[3] = USB3_PORT_DEFAULT(OC3),		// Type-A Port (board)
+			}"
+		end
 		device ref i2c0		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
diff --git a/src/mainboard/google/glados/variants/caroline/overridetree.cb b/src/mainboard/google/glados/variants/caroline/overridetree.cb
index 6ea484520f..fd6ded475f 100644
--- a/src/mainboard/google/glados/variants/caroline/overridetree.cb
+++ b/src/mainboard/google/glados/variants/caroline/overridetree.cb
@@ -9,14 +9,6 @@ chip soc/intel/skylake
 	register "SlowSlewRateForGt" = "3"	# Fast/16
 	register "SlowSlewRateForSa" = "0"	# Fast/2
 
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-C Port (main)
-	register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)"	# Type-C Port (sub)
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (main)
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (sub)
-
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,	// touchpad
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,	// touchscreen
@@ -38,6 +30,19 @@ chip soc/intel/skylake
 	register "tcc_offset" = "10"
 
 	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP),	// Type-C Port (main)
+				[1] = USB2_PORT_MAX(OC_SKIP),	// Type-C Port (sub)
+				[2] = USB2_PORT_MID(OC_SKIP),	// Bluetooth
+				[6] = USB2_PORT_FLEX(OC_SKIP),	// Camera
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port (main)
+				[1] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port (sub)
+			}"
+		end
 		device ref i2c0		on
 			chip drivers/i2c/generic
 				register "hid" = ""ATML0001""
diff --git a/src/mainboard/google/glados/variants/cave/overridetree.cb b/src/mainboard/google/glados/variants/cave/overridetree.cb
index 7d78d6b532..0aeb31794b 100644
--- a/src/mainboard/google/glados/variants/cave/overridetree.cb
+++ b/src/mainboard/google/glados/variants/cave/overridetree.cb
@@ -3,14 +3,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"		# 1s
 	register "PmConfigSlpSusMinAssert" = "1"	# 500ms
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C Port (board)
-	register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)"	# Type-C Port (flex)
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C Port (board)
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C Port (flex)
-
 	# PL2 override 15W
 	register "power_limits_config" = "{
 		.tdp_pl2_override = 15,
@@ -26,6 +18,19 @@ chip soc/intel/skylake
 	register "sdcard_cd_gpio" = "GPP_A7"
 
 	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_TYPE_C(OC_SKIP),	// Type-C Port (board)
+				[1] = USB2_PORT_MAX(OC_SKIP),		// Type-C Port (flex)
+				[2] = USB2_PORT_MID(OC_SKIP),		// Bluetooth
+				[6] = USB2_PORT_FLEX(OC_SKIP),		// Camera
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC_SKIP),	// Type-C Port (board)
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	// Type-C Port (flex)
+			}"
+		end
 		device ref i2c0		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
diff --git a/src/mainboard/google/glados/variants/chell/overridetree.cb b/src/mainboard/google/glados/variants/chell/overridetree.cb
index 9e4b7f0fc7..8ab7c35960 100644
--- a/src/mainboard/google/glados/variants/chell/overridetree.cb
+++ b/src/mainboard/google/glados/variants/chell/overridetree.cb
@@ -3,18 +3,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"		# 1s
 	register "PmConfigSlpSusMinAssert" = "1"	# 500ms
 
-	register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)"	# Type-C Port 2
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"		# Type-A Port
-	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# SD
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"	# Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"	# Type-A Port
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# SD
-
 	# PL2 override 15W
 	register "power_limits_config" = "{
 		.tdp_pl2_override = 15,
@@ -27,6 +15,23 @@ chip soc/intel/skylake
 	register "tcc_offset" = "10"
 
 	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_LONG(OC2),	// Type-C Port 1
+				[1] = USB2_PORT_LONG(OC3),	// Type-C Port 2
+				[2] = USB2_PORT_MID(OC_SKIP),	// Bluetooth
+				[4] = USB2_PORT_MID(OC0),	// Type-A Port
+				[6] = USB2_PORT_FLEX(OC_SKIP),	// Camera
+				[8] = USB2_PORT_MID(OC_SKIP),	// SD
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC2),		// Type-C Port 1
+				[1] = USB3_PORT_DEFAULT(OC3),		// Type-C Port 2
+				[2] = USB3_PORT_DEFAULT(OC0),		// Type-A Port
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// SD
+			}"
+		end
 		device ref i2c1		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
diff --git a/src/mainboard/google/glados/variants/glados/overridetree.cb b/src/mainboard/google/glados/variants/glados/overridetree.cb
index 3bd4e3ab53..b2d8fc0ba8 100644
--- a/src/mainboard/google/glados/variants/glados/overridetree.cb
+++ b/src/mainboard/google/glados/variants/glados/overridetree.cb
@@ -3,18 +3,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"		# 1s
 	register "PmConfigSlpSusMinAssert" = "1"	# 500ms
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port (board)
-	register "usb2_ports[1]" = "USB2_PORT_MAX(OC3)"		# Type-C Port (flex)
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"		# Type-A Port 1
-	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC1)"		# Type-A Port 2
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port (board)
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"	# Type-C Port (flex)
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"	# Type-A Port 1
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"	# Type-A Port 2
-
 	# PL2 override 15W
 	register "power_limits_config" = "{
 		.tdp_pl2_override = 15,
@@ -27,6 +15,23 @@ chip soc/intel/skylake
 	register "tcc_offset" = "10"
 
 	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_TYPE_C(OC2),	// Type-C Port (board)
+				[1] = USB2_PORT_MAX(OC3),	// Type-C Port (flex)
+				[2] = USB2_PORT_MID(OC_SKIP),	// Bluetooth
+				[4] = USB2_PORT_MID(OC0),	// Type-A Port 1
+				[6] = USB2_PORT_FLEX(OC_SKIP),	// Camera
+				[8] = USB2_PORT_MID(OC1),	// Type-A Port 2
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC2),	// Type-C Port (board)
+				[1] = USB3_PORT_DEFAULT(OC3),	// Type-C Port (flex)
+				[2] = USB3_PORT_DEFAULT(OC0),	// Type-A Port 1
+				[3] = USB3_PORT_DEFAULT(OC1),	// Type-A Port 2
+			}"
+		end
 		device ref i2c0		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
diff --git a/src/mainboard/google/glados/variants/lars/overridetree.cb b/src/mainboard/google/glados/variants/lars/overridetree.cb
index 2616044e51..1165520208 100644
--- a/src/mainboard/google/glados/variants/lars/overridetree.cb
+++ b/src/mainboard/google/glados/variants/lars/overridetree.cb
@@ -1,18 +1,23 @@
 chip soc/intel/skylake
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"		# Type-A Port (card)
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# SD
-	register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)"	# Type-A Port (board)
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Port (card)
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Port (board)
-
 	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_TYPE_C(OC0),	// Type-C Port 1
+				[1] = USB2_PORT_FLEX(OC_SKIP),	// Camera
+				[2] = USB2_PORT_MID(OC_SKIP),	// Bluetooth
+				[4] = USB2_PORT_MID(OC2),	// Type-A Port (card)
+				[5] = USB2_PORT_MID(OC_SKIP),	// SD
+				[8] = USB2_PORT_LONG(OC3),	// Type-A Port (board)
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),		// Type-C Port 1
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	// SD
+				[2] = USB3_PORT_DEFAULT(OC2),		// Type-A Port (card)
+				[3] = USB3_PORT_DEFAULT(OC3),		// Type-A Port (board)
+			}"
+		end
 		device ref i2c0		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
diff --git a/src/mainboard/google/glados/variants/sentry/overridetree.cb b/src/mainboard/google/glados/variants/sentry/overridetree.cb
index e052502514..f59108c7b8 100644
--- a/src/mainboard/google/glados/variants/sentry/overridetree.cb
+++ b/src/mainboard/google/glados/variants/sentry/overridetree.cb
@@ -1,17 +1,5 @@
 chip soc/intel/skylake
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# Type-C Port 2
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"		# Type-A Port (card)
-	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
-	register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)"	# Type-A Port (board)
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card)
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)
-
 	# I2C0 is 3.3V
 	register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
 
@@ -19,6 +7,23 @@ chip soc/intel/skylake
 	register "sdcard_cd_gpio" = "GPP_A7"
 
 	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_TYPE_C(OC0),	// Type-C Port 1
+				[1] = USB2_PORT_TYPE_C(OC1),	// Type-C Port 2
+				[2] = USB2_PORT_MID(OC_SKIP),	// Bluetooth
+				[4] = USB2_PORT_MID(OC2),	// Type-A Port (card)
+				[6] = USB2_PORT_FLEX(OC_SKIP),	// Camera
+				[8] = USB2_PORT_LONG(OC3),	// Type-A Port (board)
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	// Type-C Port 1
+				[1] = USB3_PORT_DEFAULT(OC1),	// Type-C Port 2
+				[2] = USB3_PORT_DEFAULT(OC2),	// Type-A Port (card)
+				[3] = USB3_PORT_DEFAULT(OC3),	// Type-A Port (board)
+			}"
+		end
 		device ref i2c0		on
 			chip drivers/i2c/generic
 				register "hid" = ""RAYD0001""
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 181c77b999..8b821f6ecf 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -140,15 +140,6 @@ chip soc/intel/skylake
 	register "PcieRpAdvancedErrorReporting[0]" = "1"
 	register "PcieRpLtrEnable[0]" = "1"
 
-	# USB 2.0
-	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
-	register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 2
-
-	# USB 3.0
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -231,6 +222,17 @@ chip soc/intel/skylake
 		device ref imgu			on  end
 		device ref ish			off end
 		device ref south_xhci		on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_LONG(OC0),	// Type-C Port 1
+				[2] = USB2_PORT_SHORT(OC_SKIP),	// Bluetooth
+				[4] = USB2_PORT_LONG(OC1),	// Type-C Port 2
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	// Type-C Port 1
+				[1] = USB3_PORT_DEFAULT(OC1),	// Type-C Port 2
+			}"
+
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 0317139b7c..8fbed5a853 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -130,17 +130,6 @@ chip soc/intel/skylake
 	# RP 1 uses CLK SRC 1
 	register "PcieRpClkSrcNumber[0]" = "1"
 
-	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 2
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-A Port
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -251,7 +240,22 @@ chip soc/intel/skylake
 		device ref igpu			on  end
 		device ref sa_thermal		on  end
 		device ref imgu			on  end
-		device ref south_xhci		on  end
+		device ref south_xhci		on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_LONG(OC0),	// Type-C Port 1
+				[1] = USB2_PORT_MID(OC_SKIP),	// Type-A Port
+				[2] = USB2_PORT_MID(OC_SKIP),	// Bluetooth
+				[4] = USB2_PORT_LONG(OC1),	// Type-C Port 2
+				[6] = USB2_PORT_MID(OC_SKIP),	// Type-A Port
+				[8] = USB2_PORT_MID(OC_SKIP),	// Type-A Port
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),		// Type-C Port 1
+				[1] = USB3_PORT_DEFAULT(OC1),		// Type-C Port 2
+				[2] = USB3_PORT_DEFAULT(OC_SKIP),	// Type-A Port
+			}"
+		end
 		device ref south_xdci		on  end
 		device ref thermal		on  end
 		device ref cio			on  end
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 2bb5e112c8..c851c37432 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -167,19 +167,6 @@ chip soc/intel/skylake
 	register "PcieRpAdvancedErrorReporting[8]" = "1"
 	register "PcieRpLtrEnable[8]" = "1"
 
-	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 0
-	register "usb2_ports[1]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 1
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC2)"	# Type-A Port
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Card reader
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# WiFi
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# Rear camera
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# Front camera
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 0
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 1
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Port
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader
-
 	# Touchscreen
 	register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
 
@@ -276,7 +263,24 @@ chip soc/intel/skylake
 		device ref igpu			on  end
 		device ref sa_thermal		on  end
 		device ref imgu			off end
-		device ref south_xhci		on  end
+		device ref south_xhci		on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_LONG(OC0),	// Type-C Port 0
+				[1] = USB2_PORT_LONG(OC1),	// Type-C Port 1
+				[2] = USB2_PORT_MID(OC2),	// Type-A Port
+				[3] = USB2_PORT_MID(OC_SKIP),	// Card reader
+				[4] = USB2_PORT_MID(OC_SKIP),	// WiFi
+				[5] = USB2_PORT_MID(OC_SKIP),	// Rear camera
+				[6] = USB2_PORT_MID(OC_SKIP),	// Front camera
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	// Type-C Port 0
+				[1] = USB3_PORT_DEFAULT(OC1),	// Type-C Port 1
+				[2] = USB3_PORT_DEFAULT(OC2),	// Type-A Port
+				[3] = USB3_PORT_DEFAULT(OC_SKIP), // Card reader
+			}"
+		end
 		device ref south_xdci		on  end
 		device ref thermal		on  end
 		device ref cio			off end
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 29233c9d2a..122fb153c3 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -148,18 +148,6 @@ chip soc/intel/skylake
 	# RP 1, Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpLtrEnable[0]" = "1"
 
-	register "usb2_ports[0]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_SHORT(OC2)"	# Type-A Port
-	register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 2
-	register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)"	# H1
-	register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)"	# Camera
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Port
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# LTE module
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -282,7 +270,23 @@ chip soc/intel/skylake
 		device ref igpu 		on  end
 		device ref sa_thermal 		on  end
 		device ref imgu 		on  end
-		device ref south_xhci 		on  end
+		device ref south_xhci 		on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_LONG(OC1),	// Type-C Port 1
+				[1] = USB2_PORT_SHORT(OC2),	// Type-A Port
+				[2] = USB2_PORT_SHORT(OC_SKIP),	// Bluetooth
+				[4] = USB2_PORT_LONG(OC0),	// Type-C Port 2
+				[6] = USB2_PORT_SHORT(OC_SKIP),	// H1
+				[8] = USB2_PORT_SHORT(OC_SKIP),	// Camera
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC1),		// Type-C Port 1
+				[1] = USB3_PORT_DEFAULT(OC0),		// Type-C Port 2
+				[2] = USB3_PORT_DEFAULT(OC2),		// Type-A Port
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// LTE module
+			}"
+		end
 		device ref south_xdci 		on  end
 		device ref thermal 		on  end
 		device ref cio 			on  end
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 1ef0b454ab..140f5f864b 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -147,16 +147,6 @@ chip soc/intel/skylake
 	register "PcieRpAdvancedErrorReporting[8]" = "1"
 	register "PcieRpLtrEnable[8]" = "1"
 
-	# USB 2.0
-	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
-	register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 2
-	register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)"	# pogo port
-
-	# USB 3.0
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -247,6 +237,18 @@ chip soc/intel/skylake
 		device ref sa_thermal 		on  end
 		device ref imgu 		on  end
 		device ref south_xhci		on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_LONG(OC0),	// Type-C Port 1
+				[2] = USB2_PORT_SHORT(OC_SKIP),	// Bluetooth
+				[4] = USB2_PORT_LONG(OC1),	// Type-C Port 2
+				[6] = USB2_PORT_LONG(OC_SKIP),	// pogo port
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	// Type-C Port 1
+				[1] = USB3_PORT_DEFAULT(OC1),	// Type-C Port 2
+			}"
+
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 42528cfe0e..823df7cdd0 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -137,17 +137,6 @@ chip soc/intel/skylake
 	# RP 1, Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpLtrEnable[0]" = "1"
 
-	register "usb2_ports[0]" = "USB2_PORT_SHORT(OC0)"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)"	# Type-A Port
-	register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 2
-	register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)"	# H1
-	register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)"	# Camera
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Port
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -233,6 +222,20 @@ chip soc/intel/skylake
 		device ref sa_thermal 		on  end
 		device ref imgu 		off end
 		device ref south_xhci		on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_SHORT(OC0),	// Type-C Port 1
+				[1] = USB2_PORT_LONG(OC3),	// Type-A Port
+				[2] = USB2_PORT_SHORT(OC_SKIP),	// Bluetooth
+				[4] = USB2_PORT_LONG(OC1),	// Type-C Port 2
+				[6] = USB2_PORT_SHORT(OC_SKIP),	// H1
+				[8] = USB2_PORT_SHORT(OC_SKIP),	// Camera
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	// Type-C Port 1
+				[1] = USB3_PORT_DEFAULT(OC1),	// Type-C Port 2
+				[2] = USB3_PORT_DEFAULT(OC3),	// Type-A Port
+			}"
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index fb8aad2236..e877260887 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -139,17 +139,6 @@ chip soc/intel/skylake
 	# RP 1 uses CLK SRC 1
 	register "PcieRpClkSrcNumber[0]" = "1"
 
-	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)"		# Type-C Port 2
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-A Port
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -261,7 +250,22 @@ chip soc/intel/skylake
 		device ref igpu			on  end
 		device ref sa_thermal		on  end
 		device ref imgu			on  end
-		device ref south_xhci		on  end
+		device ref south_xhci		on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_LONG(OC0),	// Type-C Port 1
+				[1] = USB2_PORT_MID(OC_SKIP),	// Type-A Port
+				[2] = USB2_PORT_MID(OC_SKIP),	// Bluetooth
+				[4] = USB2_PORT_MAX(OC1),	// Type-C Port 2
+				[6] = USB2_PORT_MID(OC_SKIP),	// Type-A Port
+				[8] = USB2_PORT_MID(OC_SKIP),	// Type-A Port
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	// Type-C Port 1
+				[1] = USB3_PORT_DEFAULT(OC1),	// Type-C Port 2
+				[2] = USB3_PORT_DEFAULT(OC_SKIP),	// Type-A Port
+			}"
+		end
 		device ref south_xdci		on  end
 		device ref thermal		on  end
 		device ref cio			on  end